📄 psocgpioint.h

📁 带触摸按键的高端电磁炉设计该方案采用CYPRESS的新器件CY8C22545,是一款专门针对中高端的家电触摸产品设计。除了集成触摸按键功能外
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#pragma	ioport	CSD2X_1SW3_DriveMode_1_ADDR:	0x10d
BYTE			CSD2X_1SW3_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW3_DriveMode_2_ADDR:	0xf
BYTE			CSD2X_1SW3_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW3_GlobalSelect_ADDR:	0xe
BYTE			CSD2X_1SW3_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW3_IntCtrl_0_ADDR:	0x10e
BYTE			CSD2X_1SW3_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW3_IntCtrl_1_ADDR:	0x10f
BYTE			CSD2X_1SW3_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW3_IntEn_ADDR:	0xd
BYTE			CSD2X_1SW3_IntEn_ADDR;
#define CSD2X_1SW3_MASK 0x10
#pragma	ioport	CSD2X_1SW3_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD2X_1SW3_MUXBusCtrl_ADDR;
// CSD2X_1SW3 Shadow defines
//   CSD2X_1SW3_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD2X_1SW3_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD2X_1SW2 address and mask defines
#pragma	ioport	CSD2X_1SW2_Data_ADDR:	0xc
BYTE			CSD2X_1SW2_Data_ADDR;
#pragma	ioport	CSD2X_1SW2_DriveMode_0_ADDR:	0x10c
BYTE			CSD2X_1SW2_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW2_DriveMode_1_ADDR:	0x10d
BYTE			CSD2X_1SW2_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW2_DriveMode_2_ADDR:	0xf
BYTE			CSD2X_1SW2_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW2_GlobalSelect_ADDR:	0xe
BYTE			CSD2X_1SW2_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW2_IntCtrl_0_ADDR:	0x10e
BYTE			CSD2X_1SW2_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW2_IntCtrl_1_ADDR:	0x10f
BYTE			CSD2X_1SW2_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW2_IntEn_ADDR:	0xd
BYTE			CSD2X_1SW2_IntEn_ADDR;
#define CSD2X_1SW2_MASK 0x20
#pragma	ioport	CSD2X_1SW2_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD2X_1SW2_MUXBusCtrl_ADDR;
// CSD2X_1SW2 Shadow defines
//   CSD2X_1SW2_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD2X_1SW2_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD2X_1SW5 address and mask defines
#pragma	ioport	CSD2X_1SW5_Data_ADDR:	0xc
BYTE			CSD2X_1SW5_Data_ADDR;
#pragma	ioport	CSD2X_1SW5_DriveMode_0_ADDR:	0x10c
BYTE			CSD2X_1SW5_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW5_DriveMode_1_ADDR:	0x10d
BYTE			CSD2X_1SW5_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW5_DriveMode_2_ADDR:	0xf
BYTE			CSD2X_1SW5_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW5_GlobalSelect_ADDR:	0xe
BYTE			CSD2X_1SW5_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW5_IntCtrl_0_ADDR:	0x10e
BYTE			CSD2X_1SW5_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW5_IntCtrl_1_ADDR:	0x10f
BYTE			CSD2X_1SW5_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW5_IntEn_ADDR:	0xd
BYTE			CSD2X_1SW5_IntEn_ADDR;
#define CSD2X_1SW5_MASK 0x40
#pragma	ioport	CSD2X_1SW5_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD2X_1SW5_MUXBusCtrl_ADDR;
// CSD2X_1SW5 Shadow defines
//   CSD2X_1SW5_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD2X_1SW5_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD2X_1SW4 address and mask defines
#pragma	ioport	CSD2X_1SW4_Data_ADDR:	0xc
BYTE			CSD2X_1SW4_Data_ADDR;
#pragma	ioport	CSD2X_1SW4_DriveMode_0_ADDR:	0x10c
BYTE			CSD2X_1SW4_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW4_DriveMode_1_ADDR:	0x10d
BYTE			CSD2X_1SW4_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW4_DriveMode_2_ADDR:	0xf
BYTE			CSD2X_1SW4_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW4_GlobalSelect_ADDR:	0xe
BYTE			CSD2X_1SW4_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW4_IntCtrl_0_ADDR:	0x10e
BYTE			CSD2X_1SW4_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW4_IntCtrl_1_ADDR:	0x10f
BYTE			CSD2X_1SW4_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW4_IntEn_ADDR:	0xd
BYTE			CSD2X_1SW4_IntEn_ADDR;
#define CSD2X_1SW4_MASK 0x80
#pragma	ioport	CSD2X_1SW4_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD2X_1SW4_MUXBusCtrl_ADDR;
// CSD2X_1SW4 Shadow defines
//   CSD2X_1SW4_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD2X_1SW4_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD2X_1SW7 address and mask defines
#pragma	ioport	CSD2X_1SW7_Data_ADDR:	0x10
BYTE			CSD2X_1SW7_Data_ADDR;
#pragma	ioport	CSD2X_1SW7_DriveMode_0_ADDR:	0x110
BYTE			CSD2X_1SW7_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW7_DriveMode_1_ADDR:	0x111
BYTE			CSD2X_1SW7_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW7_DriveMode_2_ADDR:	0x13
BYTE			CSD2X_1SW7_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW7_GlobalSelect_ADDR:	0x12
BYTE			CSD2X_1SW7_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW7_IntCtrl_0_ADDR:	0x112
BYTE			CSD2X_1SW7_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW7_IntCtrl_1_ADDR:	0x113
BYTE			CSD2X_1SW7_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW7_IntEn_ADDR:	0x11
BYTE			CSD2X_1SW7_IntEn_ADDR;
#define CSD2X_1SW7_MASK 0x1
#pragma	ioport	CSD2X_1SW7_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD2X_1SW7_MUXBusCtrl_ADDR;
// CSD2X_1SW7 Shadow defines
//   CSD2X_1SW7_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD2X_1SW7_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD2X_1SW6 address and mask defines
#pragma	ioport	CSD2X_1SW6_Data_ADDR:	0x10
BYTE			CSD2X_1SW6_Data_ADDR;
#pragma	ioport	CSD2X_1SW6_DriveMode_0_ADDR:	0x110
BYTE			CSD2X_1SW6_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW6_DriveMode_1_ADDR:	0x111
BYTE			CSD2X_1SW6_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW6_DriveMode_2_ADDR:	0x13
BYTE			CSD2X_1SW6_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW6_GlobalSelect_ADDR:	0x12
BYTE			CSD2X_1SW6_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW6_IntCtrl_0_ADDR:	0x112
BYTE			CSD2X_1SW6_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW6_IntCtrl_1_ADDR:	0x113
BYTE			CSD2X_1SW6_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW6_IntEn_ADDR:	0x11
BYTE			CSD2X_1SW6_IntEn_ADDR;
#define CSD2X_1SW6_MASK 0x2
#pragma	ioport	CSD2X_1SW6_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD2X_1SW6_MUXBusCtrl_ADDR;
// CSD2X_1SW6 Shadow defines
//   CSD2X_1SW6_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD2X_1SW6_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD2X_1SW9 address and mask defines
#pragma	ioport	CSD2X_1SW9_Data_ADDR:	0x10
BYTE			CSD2X_1SW9_Data_ADDR;
#pragma	ioport	CSD2X_1SW9_DriveMode_0_ADDR:	0x110
BYTE			CSD2X_1SW9_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW9_DriveMode_1_ADDR:	0x111
BYTE			CSD2X_1SW9_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW9_DriveMode_2_ADDR:	0x13
BYTE			CSD2X_1SW9_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW9_GlobalSelect_ADDR:	0x12
BYTE			CSD2X_1SW9_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW9_IntCtrl_0_ADDR:	0x112
BYTE			CSD2X_1SW9_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW9_IntCtrl_1_ADDR:	0x113
BYTE			CSD2X_1SW9_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW9_IntEn_ADDR:	0x11
BYTE			CSD2X_1SW9_IntEn_ADDR;
#define CSD2X_1SW9_MASK 0x4
#pragma	ioport	CSD2X_1SW9_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD2X_1SW9_MUXBusCtrl_ADDR;
// CSD2X_1SW9 Shadow defines
//   CSD2X_1SW9_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD2X_1SW9_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD2X_1SW8 address and mask defines
#pragma	ioport	CSD2X_1SW8_Data_ADDR:	0x10
BYTE			CSD2X_1SW8_Data_ADDR;
#pragma	ioport	CSD2X_1SW8_DriveMode_0_ADDR:	0x110
BYTE			CSD2X_1SW8_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW8_DriveMode_1_ADDR:	0x111
BYTE			CSD2X_1SW8_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW8_DriveMode_2_ADDR:	0x13
BYTE			CSD2X_1SW8_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW8_GlobalSelect_ADDR:	0x12
BYTE			CSD2X_1SW8_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW8_IntCtrl_0_ADDR:	0x112
BYTE			CSD2X_1SW8_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW8_IntCtrl_1_ADDR:	0x113
BYTE			CSD2X_1SW8_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW8_IntEn_ADDR:	0x11
BYTE			CSD2X_1SW8_IntEn_ADDR;
#define CSD2X_1SW8_MASK 0x8
#pragma	ioport	CSD2X_1SW8_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD2X_1SW8_MUXBusCtrl_ADDR;
// CSD2X_1SW8 Shadow defines
//   CSD2X_1SW8_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD2X_1SW8_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD2X_1SW11 address and mask defines
#pragma	ioport	CSD2X_1SW11_Data_ADDR:	0x10
BYTE			CSD2X_1SW11_Data_ADDR;
#pragma	ioport	CSD2X_1SW11_DriveMode_0_ADDR:	0x110
BYTE			CSD2X_1SW11_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW11_DriveMode_1_ADDR:	0x111
BYTE			CSD2X_1SW11_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW11_DriveMode_2_ADDR:	0x13
BYTE			CSD2X_1SW11_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW11_GlobalSelect_ADDR:	0x12
BYTE			CSD2X_1SW11_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW11_IntCtrl_0_ADDR:	0x112
BYTE			CSD2X_1SW11_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW11_IntCtrl_1_ADDR:	0x113
BYTE			CSD2X_1SW11_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW11_IntEn_ADDR:	0x11
BYTE			CSD2X_1SW11_IntEn_ADDR;
#define CSD2X_1SW11_MASK 0x10
#pragma	ioport	CSD2X_1SW11_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD2X_1SW11_MUXBusCtrl_ADDR;
// CSD2X_1SW11 Shadow defines
//   CSD2X_1SW11_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD2X_1SW11_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD2X_1SW10 address and mask defines
#pragma	ioport	CSD2X_1SW10_Data_ADDR:	0x10
BYTE			CSD2X_1SW10_Data_ADDR;
#pragma	ioport	CSD2X_1SW10_DriveMode_0_ADDR:	0x110
BYTE			CSD2X_1SW10_DriveMode_0_ADDR;
#pragma	ioport	CSD2X_1SW10_DriveMode_1_ADDR:	0x111
BYTE			CSD2X_1SW10_DriveMode_1_ADDR;
#pragma	ioport	CSD2X_1SW10_DriveMode_2_ADDR:	0x13
BYTE			CSD2X_1SW10_DriveMode_2_ADDR;
#pragma	ioport	CSD2X_1SW10_GlobalSelect_ADDR:	0x12
BYTE			CSD2X_1SW10_GlobalSelect_ADDR;
#pragma	ioport	CSD2X_1SW10_IntCtrl_0_ADDR:	0x112
BYTE			CSD2X_1SW10_IntCtrl_0_ADDR;
#pragma	ioport	CSD2X_1SW10_IntCtrl_1_ADDR:	0x113
BYTE			CSD2X_1SW10_IntCtrl_1_ADDR;
#pragma	ioport	CSD2X_1SW10_IntEn_ADDR:	0x11
BYTE			CSD2X_1SW10_IntEn_ADDR;
#define CSD2X_1SW10_MASK 0x20
#pragma	ioport	CSD2X_1SW10_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD2X_1SW10_MUXBusCtrl_ADDR;
// CSD2X_1SW10 Shadow defines
//   CSD2X_1SW10_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD2X_1SW10_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
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