📄 psocgpioint.h
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/******************************************************************************
* Generated by PSoC Designer ???
******************************************************************************/
#include <m8c.h>
// CSD2X_1Capacitor_L address and mask defines
#pragma ioport CSD2X_1Capacitor_L_Data_ADDR: 0x0
BYTE CSD2X_1Capacitor_L_Data_ADDR;
#pragma ioport CSD2X_1Capacitor_L_DriveMode_0_ADDR: 0x100
BYTE CSD2X_1Capacitor_L_DriveMode_0_ADDR;
#pragma ioport CSD2X_1Capacitor_L_DriveMode_1_ADDR: 0x101
BYTE CSD2X_1Capacitor_L_DriveMode_1_ADDR;
#pragma ioport CSD2X_1Capacitor_L_DriveMode_2_ADDR: 0x3
BYTE CSD2X_1Capacitor_L_DriveMode_2_ADDR;
#pragma ioport CSD2X_1Capacitor_L_GlobalSelect_ADDR: 0x2
BYTE CSD2X_1Capacitor_L_GlobalSelect_ADDR;
#pragma ioport CSD2X_1Capacitor_L_IntCtrl_0_ADDR: 0x102
BYTE CSD2X_1Capacitor_L_IntCtrl_0_ADDR;
#pragma ioport CSD2X_1Capacitor_L_IntCtrl_1_ADDR: 0x103
BYTE CSD2X_1Capacitor_L_IntCtrl_1_ADDR;
#pragma ioport CSD2X_1Capacitor_L_IntEn_ADDR: 0x1
BYTE CSD2X_1Capacitor_L_IntEn_ADDR;
#define CSD2X_1Capacitor_L_MASK 0x20
#pragma ioport CSD2X_1Capacitor_L_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD2X_1Capacitor_L_MUXBusCtrl_ADDR;
// CSD2X_1Capacitor_R address and mask defines
#pragma ioport CSD2X_1Capacitor_R_Data_ADDR: 0x0
BYTE CSD2X_1Capacitor_R_Data_ADDR;
#pragma ioport CSD2X_1Capacitor_R_DriveMode_0_ADDR: 0x100
BYTE CSD2X_1Capacitor_R_DriveMode_0_ADDR;
#pragma ioport CSD2X_1Capacitor_R_DriveMode_1_ADDR: 0x101
BYTE CSD2X_1Capacitor_R_DriveMode_1_ADDR;
#pragma ioport CSD2X_1Capacitor_R_DriveMode_2_ADDR: 0x3
BYTE CSD2X_1Capacitor_R_DriveMode_2_ADDR;
#pragma ioport CSD2X_1Capacitor_R_GlobalSelect_ADDR: 0x2
BYTE CSD2X_1Capacitor_R_GlobalSelect_ADDR;
#pragma ioport CSD2X_1Capacitor_R_IntCtrl_0_ADDR: 0x102
BYTE CSD2X_1Capacitor_R_IntCtrl_0_ADDR;
#pragma ioport CSD2X_1Capacitor_R_IntCtrl_1_ADDR: 0x103
BYTE CSD2X_1Capacitor_R_IntCtrl_1_ADDR;
#pragma ioport CSD2X_1Capacitor_R_IntEn_ADDR: 0x1
BYTE CSD2X_1Capacitor_R_IntEn_ADDR;
#define CSD2X_1Capacitor_R_MASK 0x80
#pragma ioport CSD2X_1Capacitor_R_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD2X_1Capacitor_R_MUXBusCtrl_ADDR;
// GlobalOutOdd_0 address and mask defines
#pragma ioport GlobalOutOdd_0_Data_ADDR: 0x4
BYTE GlobalOutOdd_0_Data_ADDR;
#pragma ioport GlobalOutOdd_0_DriveMode_0_ADDR: 0x104
BYTE GlobalOutOdd_0_DriveMode_0_ADDR;
#pragma ioport GlobalOutOdd_0_DriveMode_1_ADDR: 0x105
BYTE GlobalOutOdd_0_DriveMode_1_ADDR;
#pragma ioport GlobalOutOdd_0_DriveMode_2_ADDR: 0x7
BYTE GlobalOutOdd_0_DriveMode_2_ADDR;
#pragma ioport GlobalOutOdd_0_GlobalSelect_ADDR: 0x6
BYTE GlobalOutOdd_0_GlobalSelect_ADDR;
#pragma ioport GlobalOutOdd_0_IntCtrl_0_ADDR: 0x106
BYTE GlobalOutOdd_0_IntCtrl_0_ADDR;
#pragma ioport GlobalOutOdd_0_IntCtrl_1_ADDR: 0x107
BYTE GlobalOutOdd_0_IntCtrl_1_ADDR;
#pragma ioport GlobalOutOdd_0_IntEn_ADDR: 0x5
BYTE GlobalOutOdd_0_IntEn_ADDR;
#define GlobalOutOdd_0_MASK 0x1
#pragma ioport GlobalOutOdd_0_MUXBusCtrl_ADDR: 0x1d9
BYTE GlobalOutOdd_0_MUXBusCtrl_ADDR;
// GlobalInOdd_1 address and mask defines
#pragma ioport GlobalInOdd_1_Data_ADDR: 0x4
BYTE GlobalInOdd_1_Data_ADDR;
#pragma ioport GlobalInOdd_1_DriveMode_0_ADDR: 0x104
BYTE GlobalInOdd_1_DriveMode_0_ADDR;
#pragma ioport GlobalInOdd_1_DriveMode_1_ADDR: 0x105
BYTE GlobalInOdd_1_DriveMode_1_ADDR;
#pragma ioport GlobalInOdd_1_DriveMode_2_ADDR: 0x7
BYTE GlobalInOdd_1_DriveMode_2_ADDR;
#pragma ioport GlobalInOdd_1_GlobalSelect_ADDR: 0x6
BYTE GlobalInOdd_1_GlobalSelect_ADDR;
#pragma ioport GlobalInOdd_1_IntCtrl_0_ADDR: 0x106
BYTE GlobalInOdd_1_IntCtrl_0_ADDR;
#pragma ioport GlobalInOdd_1_IntCtrl_1_ADDR: 0x107
BYTE GlobalInOdd_1_IntCtrl_1_ADDR;
#pragma ioport GlobalInOdd_1_IntEn_ADDR: 0x5
BYTE GlobalInOdd_1_IntEn_ADDR;
#define GlobalInOdd_1_MASK 0x2
#pragma ioport GlobalInOdd_1_MUXBusCtrl_ADDR: 0x1d9
BYTE GlobalInOdd_1_MUXBusCtrl_ADDR;
// GlobalOutOdd_2 address and mask defines
#pragma ioport GlobalOutOdd_2_Data_ADDR: 0x4
BYTE GlobalOutOdd_2_Data_ADDR;
#pragma ioport GlobalOutOdd_2_DriveMode_0_ADDR: 0x104
BYTE GlobalOutOdd_2_DriveMode_0_ADDR;
#pragma ioport GlobalOutOdd_2_DriveMode_1_ADDR: 0x105
BYTE GlobalOutOdd_2_DriveMode_1_ADDR;
#pragma ioport GlobalOutOdd_2_DriveMode_2_ADDR: 0x7
BYTE GlobalOutOdd_2_DriveMode_2_ADDR;
#pragma ioport GlobalOutOdd_2_GlobalSelect_ADDR: 0x6
BYTE GlobalOutOdd_2_GlobalSelect_ADDR;
#pragma ioport GlobalOutOdd_2_IntCtrl_0_ADDR: 0x106
BYTE GlobalOutOdd_2_IntCtrl_0_ADDR;
#pragma ioport GlobalOutOdd_2_IntCtrl_1_ADDR: 0x107
BYTE GlobalOutOdd_2_IntCtrl_1_ADDR;
#pragma ioport GlobalOutOdd_2_IntEn_ADDR: 0x5
BYTE GlobalOutOdd_2_IntEn_ADDR;
#define GlobalOutOdd_2_MASK 0x4
#pragma ioport GlobalOutOdd_2_MUXBusCtrl_ADDR: 0x1d9
BYTE GlobalOutOdd_2_MUXBusCtrl_ADDR;
// GlobalOutOdd_3 address and mask defines
#pragma ioport GlobalOutOdd_3_Data_ADDR: 0x4
BYTE GlobalOutOdd_3_Data_ADDR;
#pragma ioport GlobalOutOdd_3_DriveMode_0_ADDR: 0x104
BYTE GlobalOutOdd_3_DriveMode_0_ADDR;
#pragma ioport GlobalOutOdd_3_DriveMode_1_ADDR: 0x105
BYTE GlobalOutOdd_3_DriveMode_1_ADDR;
#pragma ioport GlobalOutOdd_3_DriveMode_2_ADDR: 0x7
BYTE GlobalOutOdd_3_DriveMode_2_ADDR;
#pragma ioport GlobalOutOdd_3_GlobalSelect_ADDR: 0x6
BYTE GlobalOutOdd_3_GlobalSelect_ADDR;
#pragma ioport GlobalOutOdd_3_IntCtrl_0_ADDR: 0x106
BYTE GlobalOutOdd_3_IntCtrl_0_ADDR;
#pragma ioport GlobalOutOdd_3_IntCtrl_1_ADDR: 0x107
BYTE GlobalOutOdd_3_IntCtrl_1_ADDR;
#pragma ioport GlobalOutOdd_3_IntEn_ADDR: 0x5
BYTE GlobalOutOdd_3_IntEn_ADDR;
#define GlobalOutOdd_3_MASK 0x8
#pragma ioport GlobalOutOdd_3_MUXBusCtrl_ADDR: 0x1d9
BYTE GlobalOutOdd_3_MUXBusCtrl_ADDR;
// GlobalOutEven_1 address and mask defines
#pragma ioport GlobalOutEven_1_Data_ADDR: 0x8
BYTE GlobalOutEven_1_Data_ADDR;
#pragma ioport GlobalOutEven_1_DriveMode_0_ADDR: 0x108
BYTE GlobalOutEven_1_DriveMode_0_ADDR;
#pragma ioport GlobalOutEven_1_DriveMode_1_ADDR: 0x109
BYTE GlobalOutEven_1_DriveMode_1_ADDR;
#pragma ioport GlobalOutEven_1_DriveMode_2_ADDR: 0xb
BYTE GlobalOutEven_1_DriveMode_2_ADDR;
#pragma ioport GlobalOutEven_1_GlobalSelect_ADDR: 0xa
BYTE GlobalOutEven_1_GlobalSelect_ADDR;
#pragma ioport GlobalOutEven_1_IntCtrl_0_ADDR: 0x10a
BYTE GlobalOutEven_1_IntCtrl_0_ADDR;
#pragma ioport GlobalOutEven_1_IntCtrl_1_ADDR: 0x10b
BYTE GlobalOutEven_1_IntCtrl_1_ADDR;
#pragma ioport GlobalOutEven_1_IntEn_ADDR: 0x9
BYTE GlobalOutEven_1_IntEn_ADDR;
#define GlobalOutEven_1_MASK 0x2
#pragma ioport GlobalOutEven_1_MUXBusCtrl_ADDR: 0x1da
BYTE GlobalOutEven_1_MUXBusCtrl_ADDR;
// GlobalOutEven_2 address and mask defines
#pragma ioport GlobalOutEven_2_Data_ADDR: 0x8
BYTE GlobalOutEven_2_Data_ADDR;
#pragma ioport GlobalOutEven_2_DriveMode_0_ADDR: 0x108
BYTE GlobalOutEven_2_DriveMode_0_ADDR;
#pragma ioport GlobalOutEven_2_DriveMode_1_ADDR: 0x109
BYTE GlobalOutEven_2_DriveMode_1_ADDR;
#pragma ioport GlobalOutEven_2_DriveMode_2_ADDR: 0xb
BYTE GlobalOutEven_2_DriveMode_2_ADDR;
#pragma ioport GlobalOutEven_2_GlobalSelect_ADDR: 0xa
BYTE GlobalOutEven_2_GlobalSelect_ADDR;
#pragma ioport GlobalOutEven_2_IntCtrl_0_ADDR: 0x10a
BYTE GlobalOutEven_2_IntCtrl_0_ADDR;
#pragma ioport GlobalOutEven_2_IntCtrl_1_ADDR: 0x10b
BYTE GlobalOutEven_2_IntCtrl_1_ADDR;
#pragma ioport GlobalOutEven_2_IntEn_ADDR: 0x9
BYTE GlobalOutEven_2_IntEn_ADDR;
#define GlobalOutEven_2_MASK 0x4
#pragma ioport GlobalOutEven_2_MUXBusCtrl_ADDR: 0x1da
BYTE GlobalOutEven_2_MUXBusCtrl_ADDR;
// GlobalOutEven_4 address and mask defines
#pragma ioport GlobalOutEven_4_Data_ADDR: 0x8
BYTE GlobalOutEven_4_Data_ADDR;
#pragma ioport GlobalOutEven_4_DriveMode_0_ADDR: 0x108
BYTE GlobalOutEven_4_DriveMode_0_ADDR;
#pragma ioport GlobalOutEven_4_DriveMode_1_ADDR: 0x109
BYTE GlobalOutEven_4_DriveMode_1_ADDR;
#pragma ioport GlobalOutEven_4_DriveMode_2_ADDR: 0xb
BYTE GlobalOutEven_4_DriveMode_2_ADDR;
#pragma ioport GlobalOutEven_4_GlobalSelect_ADDR: 0xa
BYTE GlobalOutEven_4_GlobalSelect_ADDR;
#pragma ioport GlobalOutEven_4_IntCtrl_0_ADDR: 0x10a
BYTE GlobalOutEven_4_IntCtrl_0_ADDR;
#pragma ioport GlobalOutEven_4_IntCtrl_1_ADDR: 0x10b
BYTE GlobalOutEven_4_IntCtrl_1_ADDR;
#pragma ioport GlobalOutEven_4_IntEn_ADDR: 0x9
BYTE GlobalOutEven_4_IntEn_ADDR;
#define GlobalOutEven_4_MASK 0x10
#pragma ioport GlobalOutEven_4_MUXBusCtrl_ADDR: 0x1da
BYTE GlobalOutEven_4_MUXBusCtrl_ADDR;
// CSD2X_1SW1 address and mask defines
#pragma ioport CSD2X_1SW1_Data_ADDR: 0xc
BYTE CSD2X_1SW1_Data_ADDR;
#pragma ioport CSD2X_1SW1_DriveMode_0_ADDR: 0x10c
BYTE CSD2X_1SW1_DriveMode_0_ADDR;
#pragma ioport CSD2X_1SW1_DriveMode_1_ADDR: 0x10d
BYTE CSD2X_1SW1_DriveMode_1_ADDR;
#pragma ioport CSD2X_1SW1_DriveMode_2_ADDR: 0xf
BYTE CSD2X_1SW1_DriveMode_2_ADDR;
#pragma ioport CSD2X_1SW1_GlobalSelect_ADDR: 0xe
BYTE CSD2X_1SW1_GlobalSelect_ADDR;
#pragma ioport CSD2X_1SW1_IntCtrl_0_ADDR: 0x10e
BYTE CSD2X_1SW1_IntCtrl_0_ADDR;
#pragma ioport CSD2X_1SW1_IntCtrl_1_ADDR: 0x10f
BYTE CSD2X_1SW1_IntCtrl_1_ADDR;
#pragma ioport CSD2X_1SW1_IntEn_ADDR: 0xd
BYTE CSD2X_1SW1_IntEn_ADDR;
#define CSD2X_1SW1_MASK 0x4
#pragma ioport CSD2X_1SW1_MUXBusCtrl_ADDR: 0x1db
BYTE CSD2X_1SW1_MUXBusCtrl_ADDR;
// CSD2X_1SW1 Shadow defines
// CSD2X_1SW1_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD2X_1SW1_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD2X_1SW0 address and mask defines
#pragma ioport CSD2X_1SW0_Data_ADDR: 0xc
BYTE CSD2X_1SW0_Data_ADDR;
#pragma ioport CSD2X_1SW0_DriveMode_0_ADDR: 0x10c
BYTE CSD2X_1SW0_DriveMode_0_ADDR;
#pragma ioport CSD2X_1SW0_DriveMode_1_ADDR: 0x10d
BYTE CSD2X_1SW0_DriveMode_1_ADDR;
#pragma ioport CSD2X_1SW0_DriveMode_2_ADDR: 0xf
BYTE CSD2X_1SW0_DriveMode_2_ADDR;
#pragma ioport CSD2X_1SW0_GlobalSelect_ADDR: 0xe
BYTE CSD2X_1SW0_GlobalSelect_ADDR;
#pragma ioport CSD2X_1SW0_IntCtrl_0_ADDR: 0x10e
BYTE CSD2X_1SW0_IntCtrl_0_ADDR;
#pragma ioport CSD2X_1SW0_IntCtrl_1_ADDR: 0x10f
BYTE CSD2X_1SW0_IntCtrl_1_ADDR;
#pragma ioport CSD2X_1SW0_IntEn_ADDR: 0xd
BYTE CSD2X_1SW0_IntEn_ADDR;
#define CSD2X_1SW0_MASK 0x8
#pragma ioport CSD2X_1SW0_MUXBusCtrl_ADDR: 0x1db
BYTE CSD2X_1SW0_MUXBusCtrl_ADDR;
// CSD2X_1SW0 Shadow defines
// CSD2X_1SW0_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD2X_1SW0_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD2X_1SW3 address and mask defines
#pragma ioport CSD2X_1SW3_Data_ADDR: 0xc
BYTE CSD2X_1SW3_Data_ADDR;
#pragma ioport CSD2X_1SW3_DriveMode_0_ADDR: 0x10c
BYTE CSD2X_1SW3_DriveMode_0_ADDR;
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