📄 psocgpioint.inc
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; Generated by PSoC Designer ???
;
; CSD2X_1Capacitor_L address and mask equates
CSD2X_1Capacitor_L_Data_ADDR: equ 0h
CSD2X_1Capacitor_L_DriveMode_0_ADDR: equ 100h
CSD2X_1Capacitor_L_DriveMode_1_ADDR: equ 101h
CSD2X_1Capacitor_L_DriveMode_2_ADDR: equ 3h
CSD2X_1Capacitor_L_GlobalSelect_ADDR: equ 2h
CSD2X_1Capacitor_L_IntCtrl_0_ADDR: equ 102h
CSD2X_1Capacitor_L_IntCtrl_1_ADDR: equ 103h
CSD2X_1Capacitor_L_IntEn_ADDR: equ 1h
CSD2X_1Capacitor_L_MASK: equ 20h
CSD2X_1Capacitor_L_MUXBusCtrl_ADDR: equ 1d8h
; CSD2X_1Capacitor_R address and mask equates
CSD2X_1Capacitor_R_Data_ADDR: equ 0h
CSD2X_1Capacitor_R_DriveMode_0_ADDR: equ 100h
CSD2X_1Capacitor_R_DriveMode_1_ADDR: equ 101h
CSD2X_1Capacitor_R_DriveMode_2_ADDR: equ 3h
CSD2X_1Capacitor_R_GlobalSelect_ADDR: equ 2h
CSD2X_1Capacitor_R_IntCtrl_0_ADDR: equ 102h
CSD2X_1Capacitor_R_IntCtrl_1_ADDR: equ 103h
CSD2X_1Capacitor_R_IntEn_ADDR: equ 1h
CSD2X_1Capacitor_R_MASK: equ 80h
CSD2X_1Capacitor_R_MUXBusCtrl_ADDR: equ 1d8h
; GlobalOutOdd_0 address and mask equates
GlobalOutOdd_0_Data_ADDR: equ 4h
GlobalOutOdd_0_DriveMode_0_ADDR: equ 104h
GlobalOutOdd_0_DriveMode_1_ADDR: equ 105h
GlobalOutOdd_0_DriveMode_2_ADDR: equ 7h
GlobalOutOdd_0_GlobalSelect_ADDR: equ 6h
GlobalOutOdd_0_IntCtrl_0_ADDR: equ 106h
GlobalOutOdd_0_IntCtrl_1_ADDR: equ 107h
GlobalOutOdd_0_IntEn_ADDR: equ 5h
GlobalOutOdd_0_MASK: equ 1h
GlobalOutOdd_0_MUXBusCtrl_ADDR: equ 1d9h
; GlobalInOdd_1 address and mask equates
GlobalInOdd_1_Data_ADDR: equ 4h
GlobalInOdd_1_DriveMode_0_ADDR: equ 104h
GlobalInOdd_1_DriveMode_1_ADDR: equ 105h
GlobalInOdd_1_DriveMode_2_ADDR: equ 7h
GlobalInOdd_1_GlobalSelect_ADDR: equ 6h
GlobalInOdd_1_IntCtrl_0_ADDR: equ 106h
GlobalInOdd_1_IntCtrl_1_ADDR: equ 107h
GlobalInOdd_1_IntEn_ADDR: equ 5h
GlobalInOdd_1_MASK: equ 2h
GlobalInOdd_1_MUXBusCtrl_ADDR: equ 1d9h
; GlobalOutOdd_2 address and mask equates
GlobalOutOdd_2_Data_ADDR: equ 4h
GlobalOutOdd_2_DriveMode_0_ADDR: equ 104h
GlobalOutOdd_2_DriveMode_1_ADDR: equ 105h
GlobalOutOdd_2_DriveMode_2_ADDR: equ 7h
GlobalOutOdd_2_GlobalSelect_ADDR: equ 6h
GlobalOutOdd_2_IntCtrl_0_ADDR: equ 106h
GlobalOutOdd_2_IntCtrl_1_ADDR: equ 107h
GlobalOutOdd_2_IntEn_ADDR: equ 5h
GlobalOutOdd_2_MASK: equ 4h
GlobalOutOdd_2_MUXBusCtrl_ADDR: equ 1d9h
; GlobalOutOdd_3 address and mask equates
GlobalOutOdd_3_Data_ADDR: equ 4h
GlobalOutOdd_3_DriveMode_0_ADDR: equ 104h
GlobalOutOdd_3_DriveMode_1_ADDR: equ 105h
GlobalOutOdd_3_DriveMode_2_ADDR: equ 7h
GlobalOutOdd_3_GlobalSelect_ADDR: equ 6h
GlobalOutOdd_3_IntCtrl_0_ADDR: equ 106h
GlobalOutOdd_3_IntCtrl_1_ADDR: equ 107h
GlobalOutOdd_3_IntEn_ADDR: equ 5h
GlobalOutOdd_3_MASK: equ 8h
GlobalOutOdd_3_MUXBusCtrl_ADDR: equ 1d9h
; GlobalOutEven_1 address and mask equates
GlobalOutEven_1_Data_ADDR: equ 8h
GlobalOutEven_1_DriveMode_0_ADDR: equ 108h
GlobalOutEven_1_DriveMode_1_ADDR: equ 109h
GlobalOutEven_1_DriveMode_2_ADDR: equ bh
GlobalOutEven_1_GlobalSelect_ADDR: equ ah
GlobalOutEven_1_IntCtrl_0_ADDR: equ 10ah
GlobalOutEven_1_IntCtrl_1_ADDR: equ 10bh
GlobalOutEven_1_IntEn_ADDR: equ 9h
GlobalOutEven_1_MASK: equ 2h
GlobalOutEven_1_MUXBusCtrl_ADDR: equ 1dah
; GlobalOutEven_2 address and mask equates
GlobalOutEven_2_Data_ADDR: equ 8h
GlobalOutEven_2_DriveMode_0_ADDR: equ 108h
GlobalOutEven_2_DriveMode_1_ADDR: equ 109h
GlobalOutEven_2_DriveMode_2_ADDR: equ bh
GlobalOutEven_2_GlobalSelect_ADDR: equ ah
GlobalOutEven_2_IntCtrl_0_ADDR: equ 10ah
GlobalOutEven_2_IntCtrl_1_ADDR: equ 10bh
GlobalOutEven_2_IntEn_ADDR: equ 9h
GlobalOutEven_2_MASK: equ 4h
GlobalOutEven_2_MUXBusCtrl_ADDR: equ 1dah
; GlobalOutEven_4 address and mask equates
GlobalOutEven_4_Data_ADDR: equ 8h
GlobalOutEven_4_DriveMode_0_ADDR: equ 108h
GlobalOutEven_4_DriveMode_1_ADDR: equ 109h
GlobalOutEven_4_DriveMode_2_ADDR: equ bh
GlobalOutEven_4_GlobalSelect_ADDR: equ ah
GlobalOutEven_4_IntCtrl_0_ADDR: equ 10ah
GlobalOutEven_4_IntCtrl_1_ADDR: equ 10bh
GlobalOutEven_4_IntEn_ADDR: equ 9h
GlobalOutEven_4_MASK: equ 10h
GlobalOutEven_4_MUXBusCtrl_ADDR: equ 1dah
; CSD2X_1SW1 address and mask equates
CSD2X_1SW1_Data_ADDR: equ ch
CSD2X_1SW1_DriveMode_0_ADDR: equ 10ch
CSD2X_1SW1_DriveMode_1_ADDR: equ 10dh
CSD2X_1SW1_DriveMode_2_ADDR: equ fh
CSD2X_1SW1_GlobalSelect_ADDR: equ eh
CSD2X_1SW1_IntCtrl_0_ADDR: equ 10eh
CSD2X_1SW1_IntCtrl_1_ADDR: equ 10fh
CSD2X_1SW1_IntEn_ADDR: equ dh
CSD2X_1SW1_MASK: equ 4h
CSD2X_1SW1_MUXBusCtrl_ADDR: equ 1dbh
; CSD2X_1SW1_Data access macros
; GetCSD2X_1SW1_Data macro, return in a
macro GetCSD2X_1SW1_Data
mov a,[Port_3_Data_SHADE]
and a, 4h
endm
; SetCSD2X_1SW1_Data macro
macro SetCSD2X_1SW1_Data
or [Port_3_Data_SHADE], 4h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW1_Data_ADDR], a
endm
; ClearCSD2X_1SW1_Data macro
macro ClearCSD2X_1SW1_Data
and [Port_3_Data_SHADE], ~4h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW1_Data_ADDR], a
endm
; CSD2X_1SW0 address and mask equates
CSD2X_1SW0_Data_ADDR: equ ch
CSD2X_1SW0_DriveMode_0_ADDR: equ 10ch
CSD2X_1SW0_DriveMode_1_ADDR: equ 10dh
CSD2X_1SW0_DriveMode_2_ADDR: equ fh
CSD2X_1SW0_GlobalSelect_ADDR: equ eh
CSD2X_1SW0_IntCtrl_0_ADDR: equ 10eh
CSD2X_1SW0_IntCtrl_1_ADDR: equ 10fh
CSD2X_1SW0_IntEn_ADDR: equ dh
CSD2X_1SW0_MASK: equ 8h
CSD2X_1SW0_MUXBusCtrl_ADDR: equ 1dbh
; CSD2X_1SW0_Data access macros
; GetCSD2X_1SW0_Data macro, return in a
macro GetCSD2X_1SW0_Data
mov a,[Port_3_Data_SHADE]
and a, 8h
endm
; SetCSD2X_1SW0_Data macro
macro SetCSD2X_1SW0_Data
or [Port_3_Data_SHADE], 8h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW0_Data_ADDR], a
endm
; ClearCSD2X_1SW0_Data macro
macro ClearCSD2X_1SW0_Data
and [Port_3_Data_SHADE], ~8h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW0_Data_ADDR], a
endm
; CSD2X_1SW3 address and mask equates
CSD2X_1SW3_Data_ADDR: equ ch
CSD2X_1SW3_DriveMode_0_ADDR: equ 10ch
CSD2X_1SW3_DriveMode_1_ADDR: equ 10dh
CSD2X_1SW3_DriveMode_2_ADDR: equ fh
CSD2X_1SW3_GlobalSelect_ADDR: equ eh
CSD2X_1SW3_IntCtrl_0_ADDR: equ 10eh
CSD2X_1SW3_IntCtrl_1_ADDR: equ 10fh
CSD2X_1SW3_IntEn_ADDR: equ dh
CSD2X_1SW3_MASK: equ 10h
CSD2X_1SW3_MUXBusCtrl_ADDR: equ 1dbh
; CSD2X_1SW3_Data access macros
; GetCSD2X_1SW3_Data macro, return in a
macro GetCSD2X_1SW3_Data
mov a,[Port_3_Data_SHADE]
and a, 10h
endm
; SetCSD2X_1SW3_Data macro
macro SetCSD2X_1SW3_Data
or [Port_3_Data_SHADE], 10h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW3_Data_ADDR], a
endm
; ClearCSD2X_1SW3_Data macro
macro ClearCSD2X_1SW3_Data
and [Port_3_Data_SHADE], ~10h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW3_Data_ADDR], a
endm
; CSD2X_1SW2 address and mask equates
CSD2X_1SW2_Data_ADDR: equ ch
CSD2X_1SW2_DriveMode_0_ADDR: equ 10ch
CSD2X_1SW2_DriveMode_1_ADDR: equ 10dh
CSD2X_1SW2_DriveMode_2_ADDR: equ fh
CSD2X_1SW2_GlobalSelect_ADDR: equ eh
CSD2X_1SW2_IntCtrl_0_ADDR: equ 10eh
CSD2X_1SW2_IntCtrl_1_ADDR: equ 10fh
CSD2X_1SW2_IntEn_ADDR: equ dh
CSD2X_1SW2_MASK: equ 20h
CSD2X_1SW2_MUXBusCtrl_ADDR: equ 1dbh
; CSD2X_1SW2_Data access macros
; GetCSD2X_1SW2_Data macro, return in a
macro GetCSD2X_1SW2_Data
mov a,[Port_3_Data_SHADE]
and a, 20h
endm
; SetCSD2X_1SW2_Data macro
macro SetCSD2X_1SW2_Data
or [Port_3_Data_SHADE], 20h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW2_Data_ADDR], a
endm
; ClearCSD2X_1SW2_Data macro
macro ClearCSD2X_1SW2_Data
and [Port_3_Data_SHADE], ~20h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW2_Data_ADDR], a
endm
; CSD2X_1SW5 address and mask equates
CSD2X_1SW5_Data_ADDR: equ ch
CSD2X_1SW5_DriveMode_0_ADDR: equ 10ch
CSD2X_1SW5_DriveMode_1_ADDR: equ 10dh
CSD2X_1SW5_DriveMode_2_ADDR: equ fh
CSD2X_1SW5_GlobalSelect_ADDR: equ eh
CSD2X_1SW5_IntCtrl_0_ADDR: equ 10eh
CSD2X_1SW5_IntCtrl_1_ADDR: equ 10fh
CSD2X_1SW5_IntEn_ADDR: equ dh
CSD2X_1SW5_MASK: equ 40h
CSD2X_1SW5_MUXBusCtrl_ADDR: equ 1dbh
; CSD2X_1SW5_Data access macros
; GetCSD2X_1SW5_Data macro, return in a
macro GetCSD2X_1SW5_Data
mov a,[Port_3_Data_SHADE]
and a, 40h
endm
; SetCSD2X_1SW5_Data macro
macro SetCSD2X_1SW5_Data
or [Port_3_Data_SHADE], 40h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW5_Data_ADDR], a
endm
; ClearCSD2X_1SW5_Data macro
macro ClearCSD2X_1SW5_Data
and [Port_3_Data_SHADE], ~40h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW5_Data_ADDR], a
endm
; CSD2X_1SW4 address and mask equates
CSD2X_1SW4_Data_ADDR: equ ch
CSD2X_1SW4_DriveMode_0_ADDR: equ 10ch
CSD2X_1SW4_DriveMode_1_ADDR: equ 10dh
CSD2X_1SW4_DriveMode_2_ADDR: equ fh
CSD2X_1SW4_GlobalSelect_ADDR: equ eh
CSD2X_1SW4_IntCtrl_0_ADDR: equ 10eh
CSD2X_1SW4_IntCtrl_1_ADDR: equ 10fh
CSD2X_1SW4_IntEn_ADDR: equ dh
CSD2X_1SW4_MASK: equ 80h
CSD2X_1SW4_MUXBusCtrl_ADDR: equ 1dbh
; CSD2X_1SW4_Data access macros
; GetCSD2X_1SW4_Data macro, return in a
macro GetCSD2X_1SW4_Data
mov a,[Port_3_Data_SHADE]
and a, 80h
endm
; SetCSD2X_1SW4_Data macro
macro SetCSD2X_1SW4_Data
or [Port_3_Data_SHADE], 80h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW4_Data_ADDR], a
endm
; ClearCSD2X_1SW4_Data macro
macro ClearCSD2X_1SW4_Data
and [Port_3_Data_SHADE], ~80h
mov a, [Port_3_Data_SHADE]
mov reg[CSD2X_1SW4_Data_ADDR], a
endm
; CSD2X_1SW7 address and mask equates
CSD2X_1SW7_Data_ADDR: equ 10h
CSD2X_1SW7_DriveMode_0_ADDR: equ 110h
CSD2X_1SW7_DriveMode_1_ADDR: equ 111h
CSD2X_1SW7_DriveMode_2_ADDR: equ 13h
CSD2X_1SW7_GlobalSelect_ADDR: equ 12h
CSD2X_1SW7_IntCtrl_0_ADDR: equ 112h
CSD2X_1SW7_IntCtrl_1_ADDR: equ 113h
CSD2X_1SW7_IntEn_ADDR: equ 11h
CSD2X_1SW7_MASK: equ 1h
CSD2X_1SW7_MUXBusCtrl_ADDR: equ 1ech
; CSD2X_1SW7_Data access macros
; GetCSD2X_1SW7_Data macro, return in a
macro GetCSD2X_1SW7_Data
mov a,[Port_4_Data_SHADE]
and a, 1h
endm
; SetCSD2X_1SW7_Data macro
macro SetCSD2X_1SW7_Data
or [Port_4_Data_SHADE], 1h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW7_Data_ADDR], a
endm
; ClearCSD2X_1SW7_Data macro
macro ClearCSD2X_1SW7_Data
and [Port_4_Data_SHADE], ~1h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW7_Data_ADDR], a
endm
; CSD2X_1SW6 address and mask equates
CSD2X_1SW6_Data_ADDR: equ 10h
CSD2X_1SW6_DriveMode_0_ADDR: equ 110h
CSD2X_1SW6_DriveMode_1_ADDR: equ 111h
CSD2X_1SW6_DriveMode_2_ADDR: equ 13h
CSD2X_1SW6_GlobalSelect_ADDR: equ 12h
CSD2X_1SW6_IntCtrl_0_ADDR: equ 112h
CSD2X_1SW6_IntCtrl_1_ADDR: equ 113h
CSD2X_1SW6_IntEn_ADDR: equ 11h
CSD2X_1SW6_MASK: equ 2h
CSD2X_1SW6_MUXBusCtrl_ADDR: equ 1ech
; CSD2X_1SW6_Data access macros
; GetCSD2X_1SW6_Data macro, return in a
macro GetCSD2X_1SW6_Data
mov a,[Port_4_Data_SHADE]
and a, 2h
endm
; SetCSD2X_1SW6_Data macro
macro SetCSD2X_1SW6_Data
or [Port_4_Data_SHADE], 2h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW6_Data_ADDR], a
endm
; ClearCSD2X_1SW6_Data macro
macro ClearCSD2X_1SW6_Data
and [Port_4_Data_SHADE], ~2h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW6_Data_ADDR], a
endm
; CSD2X_1SW9 address and mask equates
CSD2X_1SW9_Data_ADDR: equ 10h
CSD2X_1SW9_DriveMode_0_ADDR: equ 110h
CSD2X_1SW9_DriveMode_1_ADDR: equ 111h
CSD2X_1SW9_DriveMode_2_ADDR: equ 13h
CSD2X_1SW9_GlobalSelect_ADDR: equ 12h
CSD2X_1SW9_IntCtrl_0_ADDR: equ 112h
CSD2X_1SW9_IntCtrl_1_ADDR: equ 113h
CSD2X_1SW9_IntEn_ADDR: equ 11h
CSD2X_1SW9_MASK: equ 4h
CSD2X_1SW9_MUXBusCtrl_ADDR: equ 1ech
; CSD2X_1SW9_Data access macros
; GetCSD2X_1SW9_Data macro, return in a
macro GetCSD2X_1SW9_Data
mov a,[Port_4_Data_SHADE]
and a, 4h
endm
; SetCSD2X_1SW9_Data macro
macro SetCSD2X_1SW9_Data
or [Port_4_Data_SHADE], 4h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW9_Data_ADDR], a
endm
; ClearCSD2X_1SW9_Data macro
macro ClearCSD2X_1SW9_Data
and [Port_4_Data_SHADE], ~4h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW9_Data_ADDR], a
endm
; CSD2X_1SW8 address and mask equates
CSD2X_1SW8_Data_ADDR: equ 10h
CSD2X_1SW8_DriveMode_0_ADDR: equ 110h
CSD2X_1SW8_DriveMode_1_ADDR: equ 111h
CSD2X_1SW8_DriveMode_2_ADDR: equ 13h
CSD2X_1SW8_GlobalSelect_ADDR: equ 12h
CSD2X_1SW8_IntCtrl_0_ADDR: equ 112h
CSD2X_1SW8_IntCtrl_1_ADDR: equ 113h
CSD2X_1SW8_IntEn_ADDR: equ 11h
CSD2X_1SW8_MASK: equ 8h
CSD2X_1SW8_MUXBusCtrl_ADDR: equ 1ech
; CSD2X_1SW8_Data access macros
; GetCSD2X_1SW8_Data macro, return in a
macro GetCSD2X_1SW8_Data
mov a,[Port_4_Data_SHADE]
and a, 8h
endm
; SetCSD2X_1SW8_Data macro
macro SetCSD2X_1SW8_Data
or [Port_4_Data_SHADE], 8h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW8_Data_ADDR], a
endm
; ClearCSD2X_1SW8_Data macro
macro ClearCSD2X_1SW8_Data
and [Port_4_Data_SHADE], ~8h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW8_Data_ADDR], a
endm
; CSD2X_1SW11 address and mask equates
CSD2X_1SW11_Data_ADDR: equ 10h
CSD2X_1SW11_DriveMode_0_ADDR: equ 110h
CSD2X_1SW11_DriveMode_1_ADDR: equ 111h
CSD2X_1SW11_DriveMode_2_ADDR: equ 13h
CSD2X_1SW11_GlobalSelect_ADDR: equ 12h
CSD2X_1SW11_IntCtrl_0_ADDR: equ 112h
CSD2X_1SW11_IntCtrl_1_ADDR: equ 113h
CSD2X_1SW11_IntEn_ADDR: equ 11h
CSD2X_1SW11_MASK: equ 10h
CSD2X_1SW11_MUXBusCtrl_ADDR: equ 1ech
; CSD2X_1SW11_Data access macros
; GetCSD2X_1SW11_Data macro, return in a
macro GetCSD2X_1SW11_Data
mov a,[Port_4_Data_SHADE]
and a, 10h
endm
; SetCSD2X_1SW11_Data macro
macro SetCSD2X_1SW11_Data
or [Port_4_Data_SHADE], 10h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW11_Data_ADDR], a
endm
; ClearCSD2X_1SW11_Data macro
macro ClearCSD2X_1SW11_Data
and [Port_4_Data_SHADE], ~10h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW11_Data_ADDR], a
endm
; CSD2X_1SW10 address and mask equates
CSD2X_1SW10_Data_ADDR: equ 10h
CSD2X_1SW10_DriveMode_0_ADDR: equ 110h
CSD2X_1SW10_DriveMode_1_ADDR: equ 111h
CSD2X_1SW10_DriveMode_2_ADDR: equ 13h
CSD2X_1SW10_GlobalSelect_ADDR: equ 12h
CSD2X_1SW10_IntCtrl_0_ADDR: equ 112h
CSD2X_1SW10_IntCtrl_1_ADDR: equ 113h
CSD2X_1SW10_IntEn_ADDR: equ 11h
CSD2X_1SW10_MASK: equ 20h
CSD2X_1SW10_MUXBusCtrl_ADDR: equ 1ech
; CSD2X_1SW10_Data access macros
; GetCSD2X_1SW10_Data macro, return in a
macro GetCSD2X_1SW10_Data
mov a,[Port_4_Data_SHADE]
and a, 20h
endm
; SetCSD2X_1SW10_Data macro
macro SetCSD2X_1SW10_Data
or [Port_4_Data_SHADE], 20h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW10_Data_ADDR], a
endm
; ClearCSD2X_1SW10_Data macro
macro ClearCSD2X_1SW10_Data
and [Port_4_Data_SHADE], ~20h
mov a, [Port_4_Data_SHADE]
mov reg[CSD2X_1SW10_Data_ADDR], a
endm
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