boot.lst
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HI-TECH Software Macro Assembler (PSoC MCU) V9.60PL1
Mon Nov 26 12:52:34 2007
1 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
2 ;
3 ;=============================================================================
4 ; FILENAME: GlobalParams.inc
5 ; DATE: 2 August 2004
6 ;
7 ; DESCRIPTION:
8 ; Constants describing many of the global parameter settings.
9 ; This file contains equates to support oscillator register initialization
10 ; for the CY8C24533
11 ;
12 ; Copyright (C) Cypress MicroSystems 2000-2004. All rights reserved.
13 ;
14 ; NOTES:
15 ; Do not modify this file. It is generated by PSoC Designer each time the
16 ; generate application function is run. The values of the parameters in this
17 ; file can be modified by changing the values of the global parameters in the
18 ; device editor.
19 ;=============================================================================
20 ;
21
22 0000 CPU_CLOCK: equ 3h ;CPU clock value
23 0000 CPU_CLOCK_MASK: equ 7h ;CPU clock mask
24 0000 CPU_CLOCK_JUST: equ 3h ;CPU clock value justified
25 0000 SELECT_32K: equ 0h ;32K select value
26 0000 SELECT_32K_MASK: equ 80h ;32K select mask
27 0000 SELECT_32K_JUST: equ 0h ;32K select value justified
28 0000 PLL_MODE: equ 0h ;PLL mode value
29 0000 PLL_MODE_MASK: equ 40h ;PLL mode mask
30 0000 PLL_MODE_JUST: equ 0h ;PLL mode value justified
31 0000 SLEEP_TIMER: equ 0h ;Sleep Timer value
32 0000 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
33 0000 SLEEP_TIMER_JUST: equ 0h ;Sleep Timer value justified
34 0000 LVD_TBEN: equ 0 ; Low Voltage Throttle-back enable value
35 0000 LVD_TBEN_MASK: equ 8 ; Low Voltage Throttle-back enable mask
36 0000 LVD_TBEN_JUST: equ 0 ; Low Voltage Throttle-back enable justified
37 0000 TRIP_VOLTAGE: equ 7h ;Trip Voltage value
38 0000 TRIP_VOLTAGE_MASK: equ 7h ;Trip Voltage mask
39 0000 TRIP_VOLTAGE_JUST: equ 7h ;Trip Voltage justified
40
41 0000 POWER_SETTING: equ 10h
42 0000 POWER_SET_5V0: equ 10h ; MASK for 5.0V operation, fast and slow
43 0000 POWER_SET_5V0_24MHZ: equ 10h ; Power Setting value for 5.0V fast
44 0000 POWER_SET_5V0_6MHZ: equ 11h ; Power Setting value for 5.0V slow
45 0000 POWER_SET_3V3: equ 08h ; MASK for 3.3V operation, fast and slow
46 0000 POWER_SET_3V3_24MHZ: equ 08h ; Power Setting value for 3.3V fast
47 0000 POWER_SET_3V3_6MHZ: equ 09h ; Power Setting value for 3.3V slow
48 0000 POWER_SET_2V7: equ 06h ; MASK for 2.7V operation, fast and slow
49 0000 POWER_SET_2V7_12MHZ: equ 04h ; MASK for 2.7V, 12MHZ operation
50 0000 POWER_SET_2V7_6MHZ: equ 02h ; MASK for 2.7V, 6MHZ operation
51 0000 POWER_SET_SLOW_IMO: equ 01h ; MASK for slow Internal Main Oscillator (IMO)
52
53 0000 COMM_RX_PRESENT: equ 0 ;1 = TRUE
54 0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
55
56 0000 CLOCK_DIV_VC1: equ 4h ;VC1 clock divider
57 0000 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
58 0000 CLOCK_DIV_VC1_JUST: equ 40h ;VC1 clock divider justified
59 0000 CLOCK_DIV_VC2: equ bh ;VC2 clock divider
60 0000 CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
61 0000 CLOCK_DIV_VC2_JUST: equ bh ;VC2 clock divider justified
62 0000 CLOCK_INPUT_VC3: equ 0h ;VC3 clock source
63 0000 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
64 0000 CLOCK_INPUT_VC3_JUST: equ 0h ;VC3 clock source justified
65 0000 CLOCK_DIV_VC3: equ 0h ;VC3 clock divider
66 0000 CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
67 0000 CLOCK_DIV_VC3_JUST: equ 0h ;VC3 clock divider justified
68 0000 ANALOG_BUFFER_PWR: equ 0h ;Analog buffer power level
69 0000 ANALOG_BUFFER_PWR_MASK: equ 1h ;Analog buffer power level mask
70 0000 ANALOG_BUFFER_PWR_JUST: equ 0h ;Analog buffer power level justified
71 0000 ANALOG_POWER: equ 5h ;Analog power control
72 0000 ANALOG_POWER_MASK: equ 7h ;Analog power control mask
73 0000 ANALOG_POWER_JUST: equ 5h ;Analog power control justified
74 0000 OP_AMP_BIAS: equ 0h ;Op amp bias level
75 0000 OP_AMP_BIAS_MASK: equ 40h ;Op amp bias level mask
76 0000 OP_AMP_BIAS_JUST: equ 0h ;Op amp bias level justified
77 0000 REF_MUX: equ 2h ;Ref mux setting
78 0000 REF_MUX_MASK: equ 38h ;Ref mux setting mask
79 0000 REF_MUX_JUST: equ 10h ;Ref mux setting justified
80 0000 AGND_BYPASS: equ 0h ;AGndBypass setting
81 0000 AGND_BYPASS_MASK: equ 40h ;AGndBypass setting mask
82 0000 AGND_BYPASS_JUST: equ 0h ;AGndBypass setting justified
83 0000 SYSCLK_SOURCE: equ (0h | 0h) ;SysClk Source setting
84 0000 SYSCLK_SOURCE_MASK: equ (4h | 2h) ;SysClk Source setting mask
85 0000 SYSCLK_SOURCE_JUST: equ (0h | 0h) ;SysClk Source setting justified
86 0000 SYSCLK_2_DISABLE: equ 0h ;SysClk*2 Disable setting
87 0000 SYSCLK_2_DISABLE_MASK: equ 1h ;SysClk*2 Disable setting mask
88 0000 SYSCLK_2_DISABLE_JUST: equ 0h ;SysClk*2 Disable setting justified
89 ;
90 ; register initial values
91 ;
92 0000 ANALOG_IO_CONTROL: equ 80h ;Analog IO Control register (ABF_CR)
93 0000 PORT_0_GLOBAL_SELECT: equ 0h ;Port 0 global select register (PRT0GS)
94 0000 PORT_0_DRIVE_0: equ 0h ;Port 0 drive mode 0 register (PRT0DM0)
95 0000 PORT_0_DRIVE_1: equ ffh ;Port 0 drive mode 1 register (PRT0DM1)
96 0000 PORT_0_DRIVE_2: equ f7h ;Port 0 drive mode 2 register (PRT0DM2)
97 0000 PORT_0_INTENABLE: equ 0h ;Port 0 interrupt enable register (PRT0IE)
98 0000 PORT_0_INTCTRL_0: equ 0h ;Port 0 interrupt control 0 register (PRT0IC0)
99 0000 PORT_0_INTCTRL_1: equ 0h ;Port 0 interrupt control 1 register (PRT0IC1)
100 0000 PORT_1_GLOBAL_SELECT: equ 0h ;Port 1 global select register (PRT1GS)
101 0000 PORT_1_DRIVE_0: equ ffh ;Port 1 drive mode 0 register (PRT1DM0)
102 0000 PORT_1_DRIVE_1: equ 3h ;Port 1 drive mode 1 register (PRT1DM1)
103 0000 PORT_1_DRIVE_2: equ 3h ;Port 1 drive mode 2 register (PRT1DM2)
104 0000 PORT_1_INTENABLE: equ 0h ;Port 1 interrupt enable register (PRT1IE)
105 0000 PORT_1_INTCTRL_0: equ 0h ;Port 1 interrupt control 0 register (PRT1IC0)
106 0000 PORT_1_INTCTRL_1: equ 0h ;Port 1 interrupt control 1 register (PRT1IC1)
107 0000 PORT_2_GLOBAL_SELECT: equ 0h ;Port 2 global select register (PRT2GS)
108 0000 PORT_2_DRIVE_0: equ f0h ;Port 2 drive mode 0 register (PRT2DM0)
109 0000 PORT_2_DRIVE_1: equ fh ;Port 2 drive mode 1 register (PRT2DM1)
110 0000 PORT_2_DRIVE_2: equ 0h ;Port 2 drive mode 2 register (PRT2DM2)
111 0000 PORT_2_INTENABLE: equ 7h ;Port 2 interrupt enable register (PRT2IE)
112 0000 PORT_2_INTCTRL_0: equ 7h ;Port 2 interrupt control 0 register (PRT2IC0)
113 0000 PORT_2_INTCTRL_1: equ 7h ;Port 2 interrupt control 1 register (PRT2IC1)
114 0000 PORT_3_GLOBAL_SELECT: equ 0h ;Port 3 global select register (PRT2GS)
115 0000 PORT_3_DRIVE_0: equ 0h ;Port 3 drive mode 0 register (PRT2DM0)
116 0000 PORT_3_DRIVE_1: equ 3h ;Port 3 drive mode 1 register (PRT2DM1)
117 0000 PORT_3_DRIVE_2: equ 3h ;Port 3 drive mode 2 register (PRT2DM2)
118 0000 PORT_3_INTENABLE: equ 0h ;Port 3 interrupt enable register (PRT2IE)
119 0000 PORT_3_INTCTRL_0: equ 0h ;Port 3 interrupt control 0 register (PRT2IC0)
120 0000 PORT_3_INTCTRL_1: equ 0h ;Port 3 interrupt control 1 register (PRT2IC1)
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- M8C24000 Microcontroller Family System Declarations
4 ;;;
5 ;;; Copyright (c) 2003-2004, Cypress MicroSystems, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress MicroSystems 24xxx Microcontroller family.
10 ;;;
11 ;;; Last Modified: August 2, 2004
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
15 ;;=============================================================================
16 ;; Definition of abbreviations used in the descriptions below
17 ;; (RW) The register or bit supports reads and writes
18 ;; (W) The register or bit is write-only
19 ;; (R) The register or bit is read-only
20 ;; (#) Access to the register is bit specific (see the family datasheet)
21 ;; (RC) The register or bit can be read, but writing a 0 will clear it,
22 ;; writing a 1 will have no effect.
23 ;;=============================================================================
24
25 ;;=============================================================================
26 ;; System Registers
27 ;;=============================================================================
28
29 ;----------------------------
30 ; Flag Register Bit Fields
31 ;----------------------------
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