boot.lst
来自「PSOC 电动自行车代码 器件采用CYPRESS新电动自行车器件CY8C245」· LST 代码 · 共 784 行 · 第 1/5 页
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503 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
504 ; M8C_EnableIntMask INT_MSKN, MASK
505 ;
506 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
507 ; and MASK is the bit set to enable or disable
508 ;----------------------------------------------------
509 ; Disable Interrupt Bit Mask(s)
510 macro M8C_DisableIntMask
511 and reg[@0], ~@1 ; disable specified interrupt enable bit
512 1DCD endm
513
514 ; Enable Interrupt Bit Mask(s)
515 macro M8C_EnableIntMask
516 or reg[@0], @1 ; enable specified interrupt enable bit
517 1DCD endm
518
519 ;----------------------------------------------------
520 ; Clear Posted Interrupt Flag Mask
521 ;
522 ; Use the following macros to clear the
523 ; bits in the Interrupt Clear registers,
524 ; INT_CLR0, INT_CLR1 or INT_CLR3.
525 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
526 ;
527 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
528 ; and MASK is the bit set to enable or disable
529 ;----------------------------------------------------
530 macro M8C_ClearIntFlag
531 mov reg[@0], ~@1 ; clear specified interrupt enable bit
532 1DCD endm
533
534 ;----------------------------------------------------
535 ; Power-On Reset & WatchDog Timer Functions
536 ;----------------------------------------------------
537 macro M8C_EnableWatchDog
538 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
539 1DCD endm
540
541 macro M8C_ClearWDT
542 mov reg[RES_WDT], 00h
543 1DCD endm
544
545 macro M8C_ClearWDTAndSleep
546 mov reg[RES_WDT], 38h
547 1DCD endm
548
549 ;----------------------------------------------------
550 ; CPU Stall for Analog PSoC Block Writes
551 ;----------------------------------------------------
552 macro M8C_Stall
553 or reg[ASY_CR], ASY_CR_SYNCEN
554 1DCD endm
555
556 macro M8C_Unstall
557 and reg[ASY_CR], ~ASY_CR_SYNCEN
558 1DCD endm
559
560 ;----------------------------------------------------
561 ; Sleep, CPU Stop & Software Reset
562 ;----------------------------------------------------
563 macro M8C_Sleep
564 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
565 ; The next instruction to be executed depends on the state of the
566 ; various interrupt enable bits. If some interrupts are enabled
567 ; and the global interrupts are disabled, the next instruction will
568 ; be the one that follows the invocation of this macro. If global
569 ; interrupts are also enabled then the next instruction will be
570 ; from the interrupt vector table. If no interrupts are enabled
571 ; then the CPU sleeps forever.
572 1DCD endm
573
574 macro M8C_Stop
575 ; In general, you probably don't want to do this, but here's how:
576 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
577 ; Next instruction to be executed is located in the interrupt
578 ; vector table entry for Power-On Reset.
579 1DCD endm
580
581 macro M8C_Reset
582 ; Restore CPU to the power-on reset state.
583 mov A, 0
584 SSC
585 ; Next non-supervisor instruction will be at interrupt vector 0.
586 1DCD endm
587
588 ;----------------------------------------------------
589 ; ImageCraft Code Compressor Actions
590 ;----------------------------------------------------
591 ; Suspend Code Compressor
592 ; Must not span a RET or RETI instruction
593 ; without resuming code compression
594 macro Suspend_CodeCompressor
595 or F, 0
596 1DCD endm
597
598 ; Resume Code Compression
599 macro Resume_CodeCompressor
600 add SP, 0
601 1DCD endm
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8SSC.INC -- M8C24xxx Microcontroller Family SSC Declarations
4 ;;;
5 ;;; Copyright (c) 2003-2004, Cypress MicroSystems, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress MicroSystems 27x6x Microcontroller family.
10 ;;;
11 ;;; Last Modified: June 8, 2004
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
15 ;----------------------------------
16 ; Common Supervisory Code Variables
17 ;----------------------------------
18 0000 bSSC_KEY1: equ F8h ; supervisory key
19 0000 bSSC_KEYSP: equ F9h ; supervisory stack ptr key
20 0000 bSSC_TABLE_TableId: equ FAh ; table ID
21
22 0000 OPER_KEY: equ 3Ah ; operation key
23
24 ;----------------------------------
25 ; SSC_Action macro command codes
26 ;----------------------------------
27 0000 FLASH_READ: equ 1 ; flash read command
28 0000 FLASH_WRITE: equ 2 ; flash write command
29 0000 FLASH_ERASE: equ 3 ; flash erase command
30 0000 PROTECT_BLOCK: equ 4 ; flash protect block command
31 0000 TABLE_READ: equ 6 ; table read command
32 0000 FLASH_CHECKSUM: equ 7 ; flash checksum calculation command
33 0000 CALIBRATE0: equ 8 ; Calibrate without checksum
34 0000 CALIBRATE1: equ 9 ; Calibrate with checksum
35
36 ;----------------------------------
37 ; SSC_Action Flash table addresses
38 ;----------------------------------
39 ; Table 0 Values
40 0000 SILICON_ID_1: equ F8h ; Table 0 first byte of silicon ID
41 0000 SILICON_ID_0: equ F9h ; Table 0 second byte of silicon ID
42
43 ; Table 1 Values
44 0000 SSCTBL1_TRIM_BGR_3V: equ F8h ; 3.3V bandgap ref voltage trim
45 0000 SSCTBL1_TRIM_IMO_3V_24MHZ: equ F9h ; 3.3V internal main oscillator trim (24MHz)
46 0000 SSCTBL1_CAL_ROOM_3V: equ FAh ; 3.3V Room Temp Calibration
47 0000 SSCTBL1_CAL_HOT_3V: equ FBh ; 3.3V Hot Temp Calibration
48 0000 SSCTBL1_TRIM_BGR_5V: equ FCh ; 5.0V bandgap ref voltage trim
49 0000 SSCTBL1_TRIM_IMO_5V_24MHZ: equ FDh ; 5.0V internal main oscillator trim (24MHz)
50 0000 SSCTBL1_CAL_ROOM_5V: equ FEh ; 5.0V Room Temp Calibration
51 0000 SSCTBL1_CAL_HOT_5V: equ FFh ; 5.0V Hot Temp Calibration
52 ; legacy names:
53 0000 VOLTAGE_TRIM_3V: equ F8h ; Table 1 3.3V bandgap ref voltage trim value
54 0000 OSCILLATOR_TRIM_3V: equ F9h ; Table 1 3.3V internal main oscillator trim valu
e
55 0000 VOLTAGE_TRIM_5V: equ FCh ; Table 1 5.0V bandgap ref voltage trim value
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