psocgpioint.h

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/******************************************************************************
*  Generated by PSoC Designer ver 4.4  b1884 : 14 Jan, 2007
******************************************************************************/
#include <m8c.h>
/*
*   PSoCGPIOINT.h
*   Data: 04 June, 2002
*   Copyright Cypress MicroSystems 2002
*
*  This file is generated by the Device Editor on Application Generation.
*  It contains equates that are useful in writing code relating to GPIO
*  related values.
*  
*  DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
*  Edits to this file will not be preserved.
*/
// HALL_2 address and mask defines
#pragma	ioport	HALL_2_Data_ADDR:	0x8
BYTE			HALL_2_Data_ADDR;
#pragma	ioport	HALL_2_DriveMode_0_ADDR:	0x108
BYTE			HALL_2_DriveMode_0_ADDR;
#pragma	ioport	HALL_2_DriveMode_1_ADDR:	0x109
BYTE			HALL_2_DriveMode_1_ADDR;
#pragma	ioport	HALL_2_DriveMode_2_ADDR:	0xb
BYTE			HALL_2_DriveMode_2_ADDR;
#pragma	ioport	HALL_2_GlobalSelect_ADDR:	0xa
BYTE			HALL_2_GlobalSelect_ADDR;
#pragma	ioport	HALL_2_IntCtrl_0_ADDR:	0x10a
BYTE			HALL_2_IntCtrl_0_ADDR;
#pragma	ioport	HALL_2_IntCtrl_1_ADDR:	0x10b
BYTE			HALL_2_IntCtrl_1_ADDR;
#pragma	ioport	HALL_2_IntEn_ADDR:	0x9
BYTE			HALL_2_IntEn_ADDR;
#define HALL_2_MASK 0x2
// HALL_1 address and mask defines
#pragma	ioport	HALL_1_Data_ADDR:	0x8
BYTE			HALL_1_Data_ADDR;
#pragma	ioport	HALL_1_DriveMode_0_ADDR:	0x108
BYTE			HALL_1_DriveMode_0_ADDR;
#pragma	ioport	HALL_1_DriveMode_1_ADDR:	0x109
BYTE			HALL_1_DriveMode_1_ADDR;
#pragma	ioport	HALL_1_DriveMode_2_ADDR:	0xb
BYTE			HALL_1_DriveMode_2_ADDR;
#pragma	ioport	HALL_1_GlobalSelect_ADDR:	0xa
BYTE			HALL_1_GlobalSelect_ADDR;
#pragma	ioport	HALL_1_IntCtrl_0_ADDR:	0x10a
BYTE			HALL_1_IntCtrl_0_ADDR;
#pragma	ioport	HALL_1_IntCtrl_1_ADDR:	0x10b
BYTE			HALL_1_IntCtrl_1_ADDR;
#pragma	ioport	HALL_1_IntEn_ADDR:	0x9
BYTE			HALL_1_IntEn_ADDR;
#define HALL_1_MASK 0x1
// HALL_3 address and mask defines
#pragma	ioport	HALL_3_Data_ADDR:	0x8
BYTE			HALL_3_Data_ADDR;
#pragma	ioport	HALL_3_DriveMode_0_ADDR:	0x108
BYTE			HALL_3_DriveMode_0_ADDR;
#pragma	ioport	HALL_3_DriveMode_1_ADDR:	0x109
BYTE			HALL_3_DriveMode_1_ADDR;
#pragma	ioport	HALL_3_DriveMode_2_ADDR:	0xb
BYTE			HALL_3_DriveMode_2_ADDR;
#pragma	ioport	HALL_3_GlobalSelect_ADDR:	0xa
BYTE			HALL_3_GlobalSelect_ADDR;
#pragma	ioport	HALL_3_IntCtrl_0_ADDR:	0x10a
BYTE			HALL_3_IntCtrl_0_ADDR;
#pragma	ioport	HALL_3_IntCtrl_1_ADDR:	0x10b
BYTE			HALL_3_IntCtrl_1_ADDR;
#pragma	ioport	HALL_3_IntEn_ADDR:	0x9
BYTE			HALL_3_IntEn_ADDR;
#define HALL_3_MASK 0x4
// ABS_SEL address and mask defines
#pragma	ioport	ABS_SEL_Data_ADDR:	0x0
BYTE			ABS_SEL_Data_ADDR;
#pragma	ioport	ABS_SEL_DriveMode_0_ADDR:	0x100
BYTE			ABS_SEL_DriveMode_0_ADDR;
#pragma	ioport	ABS_SEL_DriveMode_1_ADDR:	0x101
BYTE			ABS_SEL_DriveMode_1_ADDR;
#pragma	ioport	ABS_SEL_DriveMode_2_ADDR:	0x3
BYTE			ABS_SEL_DriveMode_2_ADDR;
#pragma	ioport	ABS_SEL_GlobalSelect_ADDR:	0x2
BYTE			ABS_SEL_GlobalSelect_ADDR;
#pragma	ioport	ABS_SEL_IntCtrl_0_ADDR:	0x102
BYTE			ABS_SEL_IntCtrl_0_ADDR;
#pragma	ioport	ABS_SEL_IntCtrl_1_ADDR:	0x103
BYTE			ABS_SEL_IntCtrl_1_ADDR;
#pragma	ioport	ABS_SEL_IntEn_ADDR:	0x1
BYTE			ABS_SEL_IntEn_ADDR;
#define ABS_SEL_MASK 0x1
// PHASE_SEL address and mask defines
#pragma	ioport	PHASE_SEL_Data_ADDR:	0x0
BYTE			PHASE_SEL_Data_ADDR;
#pragma	ioport	PHASE_SEL_DriveMode_0_ADDR:	0x100
BYTE			PHASE_SEL_DriveMode_0_ADDR;
#pragma	ioport	PHASE_SEL_DriveMode_1_ADDR:	0x101
BYTE			PHASE_SEL_DriveMode_1_ADDR;
#pragma	ioport	PHASE_SEL_DriveMode_2_ADDR:	0x3
BYTE			PHASE_SEL_DriveMode_2_ADDR;
#pragma	ioport	PHASE_SEL_GlobalSelect_ADDR:	0x2
BYTE			PHASE_SEL_GlobalSelect_ADDR;
#pragma	ioport	PHASE_SEL_IntCtrl_0_ADDR:	0x102
BYTE			PHASE_SEL_IntCtrl_0_ADDR;
#pragma	ioport	PHASE_SEL_IntCtrl_1_ADDR:	0x103
BYTE			PHASE_SEL_IntCtrl_1_ADDR;
#pragma	ioport	PHASE_SEL_IntEn_ADDR:	0x1
BYTE			PHASE_SEL_IntEn_ADDR;
#define PHASE_SEL_MASK 0x2
// CRU_SEL address and mask defines
#pragma	ioport	CRU_SEL_Data_ADDR:	0x0
BYTE			CRU_SEL_Data_ADDR;
#pragma	ioport	CRU_SEL_DriveMode_0_ADDR:	0x100
BYTE			CRU_SEL_DriveMode_0_ADDR;
#pragma	ioport	CRU_SEL_DriveMode_1_ADDR:	0x101
BYTE			CRU_SEL_DriveMode_1_ADDR;
#pragma	ioport	CRU_SEL_DriveMode_2_ADDR:	0x3
BYTE			CRU_SEL_DriveMode_2_ADDR;
#pragma	ioport	CRU_SEL_GlobalSelect_ADDR:	0x2
BYTE			CRU_SEL_GlobalSelect_ADDR;
#pragma	ioport	CRU_SEL_IntCtrl_0_ADDR:	0x102
BYTE			CRU_SEL_IntCtrl_0_ADDR;
#pragma	ioport	CRU_SEL_IntCtrl_1_ADDR:	0x103
BYTE			CRU_SEL_IntCtrl_1_ADDR;
#pragma	ioport	CRU_SEL_IntEn_ADDR:	0x1
BYTE			CRU_SEL_IntEn_ADDR;
#define CRU_SEL_MASK 0x4
// ALARM address and mask defines
#pragma	ioport	ALARM_Data_ADDR:	0x0
BYTE			ALARM_Data_ADDR;
#pragma	ioport	ALARM_DriveMode_0_ADDR:	0x100
BYTE			ALARM_DriveMode_0_ADDR;
#pragma	ioport	ALARM_DriveMode_1_ADDR:	0x101
BYTE			ALARM_DriveMode_1_ADDR;
#pragma	ioport	ALARM_DriveMode_2_ADDR:	0x3
BYTE			ALARM_DriveMode_2_ADDR;
#pragma	ioport	ALARM_GlobalSelect_ADDR:	0x2
BYTE			ALARM_GlobalSelect_ADDR;
#pragma	ioport	ALARM_IntCtrl_0_ADDR:	0x102
BYTE			ALARM_IntCtrl_0_ADDR;
#pragma	ioport	ALARM_IntCtrl_1_ADDR:	0x103
BYTE			ALARM_IntCtrl_1_ADDR;
#pragma	ioport	ALARM_IntEn_ADDR:	0x1
BYTE			ALARM_IntEn_ADDR;
#define ALARM_MASK 0x8
// BRAKE_IN address and mask defines
#pragma	ioport	BRAKE_IN_Data_ADDR:	0x0
BYTE			BRAKE_IN_Data_ADDR;
#pragma	ioport	BRAKE_IN_DriveMode_0_ADDR:	0x100
BYTE			BRAKE_IN_DriveMode_0_ADDR;
#pragma	ioport	BRAKE_IN_DriveMode_1_ADDR:	0x101
BYTE			BRAKE_IN_DriveMode_1_ADDR;
#pragma	ioport	BRAKE_IN_DriveMode_2_ADDR:	0x3
BYTE			BRAKE_IN_DriveMode_2_ADDR;
#pragma	ioport	BRAKE_IN_GlobalSelect_ADDR:	0x2
BYTE			BRAKE_IN_GlobalSelect_ADDR;
#pragma	ioport	BRAKE_IN_IntCtrl_0_ADDR:	0x102
BYTE			BRAKE_IN_IntCtrl_0_ADDR;
#pragma	ioport	BRAKE_IN_IntCtrl_1_ADDR:	0x103
BYTE			BRAKE_IN_IntCtrl_1_ADDR;
#pragma	ioport	BRAKE_IN_IntEn_ADDR:	0x1
BYTE			BRAKE_IN_IntEn_ADDR;
#define BRAKE_IN_MASK 0x10
// TS_IN address and mask defines
#pragma	ioport	TS_IN_Data_ADDR:	0x0
BYTE			TS_IN_Data_ADDR;
#pragma	ioport	TS_IN_DriveMode_0_ADDR:	0x100
BYTE			TS_IN_DriveMode_0_ADDR;
#pragma	ioport	TS_IN_DriveMode_1_ADDR:	0x101
BYTE			TS_IN_DriveMode_1_ADDR;
#pragma	ioport	TS_IN_DriveMode_2_ADDR:	0x3
BYTE			TS_IN_DriveMode_2_ADDR;
#pragma	ioport	TS_IN_GlobalSelect_ADDR:	0x2
BYTE			TS_IN_GlobalSelect_ADDR;
#pragma	ioport	TS_IN_IntCtrl_0_ADDR:	0x102
BYTE			TS_IN_IntCtrl_0_ADDR;
#pragma	ioport	TS_IN_IntCtrl_1_ADDR:	0x103
BYTE			TS_IN_IntCtrl_1_ADDR;
#pragma	ioport	TS_IN_IntEn_ADDR:	0x1
BYTE			TS_IN_IntEn_ADDR;
#define TS_IN_MASK 0x20
// BAT_V address and mask defines
#pragma	ioport	BAT_V_Data_ADDR:	0x0
BYTE			BAT_V_Data_ADDR;
#pragma	ioport	BAT_V_DriveMode_0_ADDR:	0x100
BYTE			BAT_V_DriveMode_0_ADDR;
#pragma	ioport	BAT_V_DriveMode_1_ADDR:	0x101
BYTE			BAT_V_DriveMode_1_ADDR;
#pragma	ioport	BAT_V_DriveMode_2_ADDR:	0x3
BYTE			BAT_V_DriveMode_2_ADDR;
#pragma	ioport	BAT_V_GlobalSelect_ADDR:	0x2
BYTE			BAT_V_GlobalSelect_ADDR;
#pragma	ioport	BAT_V_IntCtrl_0_ADDR:	0x102
BYTE			BAT_V_IntCtrl_0_ADDR;
#pragma	ioport	BAT_V_IntCtrl_1_ADDR:	0x103
BYTE			BAT_V_IntCtrl_1_ADDR;
#pragma	ioport	BAT_V_IntEn_ADDR:	0x1
BYTE			BAT_V_IntEn_ADDR;
#define BAT_V_MASK 0x40
// BUSI_IN address and mask defines
#pragma	ioport	BUSI_IN_Data_ADDR:	0x0
BYTE			BUSI_IN_Data_ADDR;
#pragma	ioport	BUSI_IN_DriveMode_0_ADDR:	0x100
BYTE			BUSI_IN_DriveMode_0_ADDR;
#pragma	ioport	BUSI_IN_DriveMode_1_ADDR:	0x101
BYTE			BUSI_IN_DriveMode_1_ADDR;
#pragma	ioport	BUSI_IN_DriveMode_2_ADDR:	0x3
BYTE			BUSI_IN_DriveMode_2_ADDR;
#pragma	ioport	BUSI_IN_GlobalSelect_ADDR:	0x2
BYTE			BUSI_IN_GlobalSelect_ADDR;
#pragma	ioport	BUSI_IN_IntCtrl_0_ADDR:	0x102
BYTE			BUSI_IN_IntCtrl_0_ADDR;
#pragma	ioport	BUSI_IN_IntCtrl_1_ADDR:	0x103
BYTE			BUSI_IN_IntCtrl_1_ADDR;
#pragma	ioport	BUSI_IN_IntEn_ADDR:	0x1
BYTE			BUSI_IN_IntEn_ADDR;
#define BUSI_IN_MASK 0x80
// EzI2CsSDA address and mask defines
#pragma	ioport	EzI2CsSDA_Data_ADDR:	0x4
BYTE			EzI2CsSDA_Data_ADDR;
#pragma	ioport	EzI2CsSDA_DriveMode_0_ADDR:	0x104
BYTE			EzI2CsSDA_DriveMode_0_ADDR;
#pragma	ioport	EzI2CsSDA_DriveMode_1_ADDR:	0x105
BYTE			EzI2CsSDA_DriveMode_1_ADDR;
#pragma	ioport	EzI2CsSDA_DriveMode_2_ADDR:	0x7
BYTE			EzI2CsSDA_DriveMode_2_ADDR;
#pragma	ioport	EzI2CsSDA_GlobalSelect_ADDR:	0x6
BYTE			EzI2CsSDA_GlobalSelect_ADDR;
psocgpioint.h - 源码说明

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