psocgpioint.h

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#pragma	ioport	EzI2CsSDA_IntCtrl_0_ADDR:	0x106
BYTE			EzI2CsSDA_IntCtrl_0_ADDR;
#pragma	ioport	EzI2CsSDA_IntCtrl_1_ADDR:	0x107
BYTE			EzI2CsSDA_IntCtrl_1_ADDR;
#pragma	ioport	EzI2CsSDA_IntEn_ADDR:	0x5
BYTE			EzI2CsSDA_IntEn_ADDR;
#define EzI2CsSDA_MASK 0x1
// EzI2CsSCL address and mask defines
#pragma	ioport	EzI2CsSCL_Data_ADDR:	0x4
BYTE			EzI2CsSCL_Data_ADDR;
#pragma	ioport	EzI2CsSCL_DriveMode_0_ADDR:	0x104
BYTE			EzI2CsSCL_DriveMode_0_ADDR;
#pragma	ioport	EzI2CsSCL_DriveMode_1_ADDR:	0x105
BYTE			EzI2CsSCL_DriveMode_1_ADDR;
#pragma	ioport	EzI2CsSCL_DriveMode_2_ADDR:	0x7
BYTE			EzI2CsSCL_DriveMode_2_ADDR;
#pragma	ioport	EzI2CsSCL_GlobalSelect_ADDR:	0x6
BYTE			EzI2CsSCL_GlobalSelect_ADDR;
#pragma	ioport	EzI2CsSCL_IntCtrl_0_ADDR:	0x106
BYTE			EzI2CsSCL_IntCtrl_0_ADDR;
#pragma	ioport	EzI2CsSCL_IntCtrl_1_ADDR:	0x107
BYTE			EzI2CsSCL_IntCtrl_1_ADDR;
#pragma	ioport	EzI2CsSCL_IntEn_ADDR:	0x5
BYTE			EzI2CsSCL_IntEn_ADDR;
#define EzI2CsSCL_MASK 0x2
// PWM0L address and mask defines
#pragma	ioport	PWM0L_Data_ADDR:	0x4
BYTE			PWM0L_Data_ADDR;
#pragma	ioport	PWM0L_DriveMode_0_ADDR:	0x104
BYTE			PWM0L_DriveMode_0_ADDR;
#pragma	ioport	PWM0L_DriveMode_1_ADDR:	0x105
BYTE			PWM0L_DriveMode_1_ADDR;
#pragma	ioport	PWM0L_DriveMode_2_ADDR:	0x7
BYTE			PWM0L_DriveMode_2_ADDR;
#pragma	ioport	PWM0L_GlobalSelect_ADDR:	0x6
BYTE			PWM0L_GlobalSelect_ADDR;
#pragma	ioport	PWM0L_IntCtrl_0_ADDR:	0x106
BYTE			PWM0L_IntCtrl_0_ADDR;
#pragma	ioport	PWM0L_IntCtrl_1_ADDR:	0x107
BYTE			PWM0L_IntCtrl_1_ADDR;
#pragma	ioport	PWM0L_IntEn_ADDR:	0x5
BYTE			PWM0L_IntEn_ADDR;
#define PWM0L_MASK 0x4
// PWM0H address and mask defines
#pragma	ioport	PWM0H_Data_ADDR:	0x4
BYTE			PWM0H_Data_ADDR;
#pragma	ioport	PWM0H_DriveMode_0_ADDR:	0x104
BYTE			PWM0H_DriveMode_0_ADDR;
#pragma	ioport	PWM0H_DriveMode_1_ADDR:	0x105
BYTE			PWM0H_DriveMode_1_ADDR;
#pragma	ioport	PWM0H_DriveMode_2_ADDR:	0x7
BYTE			PWM0H_DriveMode_2_ADDR;
#pragma	ioport	PWM0H_GlobalSelect_ADDR:	0x6
BYTE			PWM0H_GlobalSelect_ADDR;
#pragma	ioport	PWM0H_IntCtrl_0_ADDR:	0x106
BYTE			PWM0H_IntCtrl_0_ADDR;
#pragma	ioport	PWM0H_IntCtrl_1_ADDR:	0x107
BYTE			PWM0H_IntCtrl_1_ADDR;
#pragma	ioport	PWM0H_IntEn_ADDR:	0x5
BYTE			PWM0H_IntEn_ADDR;
#define PWM0H_MASK 0x8
// PWM1H address and mask defines
#pragma	ioport	PWM1H_Data_ADDR:	0x4
BYTE			PWM1H_Data_ADDR;
#pragma	ioport	PWM1H_DriveMode_0_ADDR:	0x104
BYTE			PWM1H_DriveMode_0_ADDR;
#pragma	ioport	PWM1H_DriveMode_1_ADDR:	0x105
BYTE			PWM1H_DriveMode_1_ADDR;
#pragma	ioport	PWM1H_DriveMode_2_ADDR:	0x7
BYTE			PWM1H_DriveMode_2_ADDR;
#pragma	ioport	PWM1H_GlobalSelect_ADDR:	0x6
BYTE			PWM1H_GlobalSelect_ADDR;
#pragma	ioport	PWM1H_IntCtrl_0_ADDR:	0x106
BYTE			PWM1H_IntCtrl_0_ADDR;
#pragma	ioport	PWM1H_IntCtrl_1_ADDR:	0x107
BYTE			PWM1H_IntCtrl_1_ADDR;
#pragma	ioport	PWM1H_IntEn_ADDR:	0x5
BYTE			PWM1H_IntEn_ADDR;
#define PWM1H_MASK 0x10
// PWM1L address and mask defines
#pragma	ioport	PWM1L_Data_ADDR:	0x4
BYTE			PWM1L_Data_ADDR;
#pragma	ioport	PWM1L_DriveMode_0_ADDR:	0x104
BYTE			PWM1L_DriveMode_0_ADDR;
#pragma	ioport	PWM1L_DriveMode_1_ADDR:	0x105
BYTE			PWM1L_DriveMode_1_ADDR;
#pragma	ioport	PWM1L_DriveMode_2_ADDR:	0x7
BYTE			PWM1L_DriveMode_2_ADDR;
#pragma	ioport	PWM1L_GlobalSelect_ADDR:	0x6
BYTE			PWM1L_GlobalSelect_ADDR;
#pragma	ioport	PWM1L_IntCtrl_0_ADDR:	0x106
BYTE			PWM1L_IntCtrl_0_ADDR;
#pragma	ioport	PWM1L_IntCtrl_1_ADDR:	0x107
BYTE			PWM1L_IntCtrl_1_ADDR;
#pragma	ioport	PWM1L_IntEn_ADDR:	0x5
BYTE			PWM1L_IntEn_ADDR;
#define PWM1L_MASK 0x20
// PWM2L address and mask defines
#pragma	ioport	PWM2L_Data_ADDR:	0x4
BYTE			PWM2L_Data_ADDR;
#pragma	ioport	PWM2L_DriveMode_0_ADDR:	0x104
BYTE			PWM2L_DriveMode_0_ADDR;
#pragma	ioport	PWM2L_DriveMode_1_ADDR:	0x105
BYTE			PWM2L_DriveMode_1_ADDR;
#pragma	ioport	PWM2L_DriveMode_2_ADDR:	0x7
BYTE			PWM2L_DriveMode_2_ADDR;
#pragma	ioport	PWM2L_GlobalSelect_ADDR:	0x6
BYTE			PWM2L_GlobalSelect_ADDR;
#pragma	ioport	PWM2L_IntCtrl_0_ADDR:	0x106
BYTE			PWM2L_IntCtrl_0_ADDR;
#pragma	ioport	PWM2L_IntCtrl_1_ADDR:	0x107
BYTE			PWM2L_IntCtrl_1_ADDR;
#pragma	ioport	PWM2L_IntEn_ADDR:	0x5
BYTE			PWM2L_IntEn_ADDR;
#define PWM2L_MASK 0x40
// PWM2H address and mask defines
#pragma	ioport	PWM2H_Data_ADDR:	0x4
BYTE			PWM2H_Data_ADDR;
#pragma	ioport	PWM2H_DriveMode_0_ADDR:	0x104
BYTE			PWM2H_DriveMode_0_ADDR;
#pragma	ioport	PWM2H_DriveMode_1_ADDR:	0x105
BYTE			PWM2H_DriveMode_1_ADDR;
#pragma	ioport	PWM2H_DriveMode_2_ADDR:	0x7
BYTE			PWM2H_DriveMode_2_ADDR;
#pragma	ioport	PWM2H_GlobalSelect_ADDR:	0x6
BYTE			PWM2H_GlobalSelect_ADDR;
#pragma	ioport	PWM2H_IntCtrl_0_ADDR:	0x106
BYTE			PWM2H_IntCtrl_0_ADDR;
#pragma	ioport	PWM2H_IntCtrl_1_ADDR:	0x107
BYTE			PWM2H_IntCtrl_1_ADDR;
#pragma	ioport	PWM2H_IntEn_ADDR:	0x5
BYTE			PWM2H_IntEn_ADDR;
#define PWM2H_MASK 0x80
// CRUISE_IN address and mask defines
#pragma	ioport	CRUISE_IN_Data_ADDR:	0x8
BYTE			CRUISE_IN_Data_ADDR;
#pragma	ioport	CRUISE_IN_DriveMode_0_ADDR:	0x108
BYTE			CRUISE_IN_DriveMode_0_ADDR;
#pragma	ioport	CRUISE_IN_DriveMode_1_ADDR:	0x109
BYTE			CRUISE_IN_DriveMode_1_ADDR;
#pragma	ioport	CRUISE_IN_DriveMode_2_ADDR:	0xb
BYTE			CRUISE_IN_DriveMode_2_ADDR;
#pragma	ioport	CRUISE_IN_GlobalSelect_ADDR:	0xa
BYTE			CRUISE_IN_GlobalSelect_ADDR;
#pragma	ioport	CRUISE_IN_IntCtrl_0_ADDR:	0x10a
BYTE			CRUISE_IN_IntCtrl_0_ADDR;
#pragma	ioport	CRUISE_IN_IntCtrl_1_ADDR:	0x10b
BYTE			CRUISE_IN_IntCtrl_1_ADDR;
#pragma	ioport	CRUISE_IN_IntEn_ADDR:	0x9
BYTE			CRUISE_IN_IntEn_ADDR;
#define CRUISE_IN_MASK 0x8
// CRUISE_DISP address and mask defines
#pragma	ioport	CRUISE_DISP_Data_ADDR:	0x8
BYTE			CRUISE_DISP_Data_ADDR;
#pragma	ioport	CRUISE_DISP_DriveMode_0_ADDR:	0x108
BYTE			CRUISE_DISP_DriveMode_0_ADDR;
#pragma	ioport	CRUISE_DISP_DriveMode_1_ADDR:	0x109
BYTE			CRUISE_DISP_DriveMode_1_ADDR;
#pragma	ioport	CRUISE_DISP_DriveMode_2_ADDR:	0xb
BYTE			CRUISE_DISP_DriveMode_2_ADDR;
#pragma	ioport	CRUISE_DISP_GlobalSelect_ADDR:	0xa
BYTE			CRUISE_DISP_GlobalSelect_ADDR;
#pragma	ioport	CRUISE_DISP_IntCtrl_0_ADDR:	0x10a
BYTE			CRUISE_DISP_IntCtrl_0_ADDR;
#pragma	ioport	CRUISE_DISP_IntCtrl_1_ADDR:	0x10b
BYTE			CRUISE_DISP_IntCtrl_1_ADDR;
#pragma	ioport	CRUISE_DISP_IntEn_ADDR:	0x9
BYTE			CRUISE_DISP_IntEn_ADDR;
#define CRUISE_DISP_MASK 0x10
// LOWBAT_DISP address and mask defines
#pragma	ioport	LOWBAT_DISP_Data_ADDR:	0x8
BYTE			LOWBAT_DISP_Data_ADDR;
#pragma	ioport	LOWBAT_DISP_DriveMode_0_ADDR:	0x108
BYTE			LOWBAT_DISP_DriveMode_0_ADDR;
#pragma	ioport	LOWBAT_DISP_DriveMode_1_ADDR:	0x109
BYTE			LOWBAT_DISP_DriveMode_1_ADDR;
#pragma	ioport	LOWBAT_DISP_DriveMode_2_ADDR:	0xb
BYTE			LOWBAT_DISP_DriveMode_2_ADDR;
#pragma	ioport	LOWBAT_DISP_GlobalSelect_ADDR:	0xa
BYTE			LOWBAT_DISP_GlobalSelect_ADDR;
#pragma	ioport	LOWBAT_DISP_IntCtrl_0_ADDR:	0x10a
BYTE			LOWBAT_DISP_IntCtrl_0_ADDR;
#pragma	ioport	LOWBAT_DISP_IntCtrl_1_ADDR:	0x10b
BYTE			LOWBAT_DISP_IntCtrl_1_ADDR;
#pragma	ioport	LOWBAT_DISP_IntEn_ADDR:	0x9
BYTE			LOWBAT_DISP_IntEn_ADDR;
#define LOWBAT_DISP_MASK 0x20
// STATE_LED address and mask defines
#pragma	ioport	STATE_LED_Data_ADDR:	0x8
BYTE			STATE_LED_Data_ADDR;
#pragma	ioport	STATE_LED_DriveMode_0_ADDR:	0x108
BYTE			STATE_LED_DriveMode_0_ADDR;
#pragma	ioport	STATE_LED_DriveMode_1_ADDR:	0x109
BYTE			STATE_LED_DriveMode_1_ADDR;
#pragma	ioport	STATE_LED_DriveMode_2_ADDR:	0xb
BYTE			STATE_LED_DriveMode_2_ADDR;
#pragma	ioport	STATE_LED_GlobalSelect_ADDR:	0xa
BYTE			STATE_LED_GlobalSelect_ADDR;
#pragma	ioport	STATE_LED_IntCtrl_0_ADDR:	0x10a
BYTE			STATE_LED_IntCtrl_0_ADDR;
#pragma	ioport	STATE_LED_IntCtrl_1_ADDR:	0x10b
BYTE			STATE_LED_IntCtrl_1_ADDR;
#pragma	ioport	STATE_LED_IntEn_ADDR:	0x9
BYTE			STATE_LED_IntEn_ADDR;
#define STATE_LED_MASK 0x40
// ABS_DISP address and mask defines
#pragma	ioport	ABS_DISP_Data_ADDR:	0x8
BYTE			ABS_DISP_Data_ADDR;
#pragma	ioport	ABS_DISP_DriveMode_0_ADDR:	0x108
BYTE			ABS_DISP_DriveMode_0_ADDR;
#pragma	ioport	ABS_DISP_DriveMode_1_ADDR:	0x109
BYTE			ABS_DISP_DriveMode_1_ADDR;
#pragma	ioport	ABS_DISP_DriveMode_2_ADDR:	0xb
BYTE			ABS_DISP_DriveMode_2_ADDR;
#pragma	ioport	ABS_DISP_GlobalSelect_ADDR:	0xa
BYTE			ABS_DISP_GlobalSelect_ADDR;
#pragma	ioport	ABS_DISP_IntCtrl_0_ADDR:	0x10a
BYTE			ABS_DISP_IntCtrl_0_ADDR;
#pragma	ioport	ABS_DISP_IntCtrl_1_ADDR:	0x10b
BYTE			ABS_DISP_IntCtrl_1_ADDR;
#pragma	ioport	ABS_DISP_IntEn_ADDR:	0x9
BYTE			ABS_DISP_IntEn_ADDR;
#define ABS_DISP_MASK 0x80
psocgpioint.h - 源码说明

本页面展示了「PSOC 电动自行车代码器件采用CYPRESS新电动自行车器件CY8C245」中的 psocgpioint.h 源码文件，采用 C头文件编程语言编写，共 449 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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