shift.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		shift8.vhd
--
-- Purpose: 	8-bit shift register with parallel load
--	
-- Created:		10/13/99 JLJ
--
-- Revised:		11-14-99 ALS
--				
--
-- **************************************************************



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


entity SHIFT8 is
	port(

	     clock        : in STD_LOGIC;    -- Clock
	     reset        : in STD_LOGIC;    -- Clear
	     data_ld      : in STD_LOGIC;    -- Data load enable
	     data_in      : in STD_LOGIC_VECTOR (7 downto 0); -- Data to load in
	     shift_in     : in STD_LOGIC;    -- Serial data in
	     shift_en     : in STD_LOGIC;    -- Shift enable
	     
	     shift_out    : out STD_LOGIC;   -- Shift serial data out
	     data_out     : out STD_LOGIC_VECTOR (7 downto 0)  -- Shifted data
		
	     );
		
end SHIFT8;




architecture DEFINITION of SHIFT8 is
-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE : std_logic := '1';

-- ******************** SIGNAL DECLARATIONS ***********************
signal data_int : STD_LOGIC_VECTOR (7 downto 0);

begin
-- ******************** Shift Process ***********************
shift_proc:process(clock, reset)
     begin
          
          -- Clear output register
          if (reset = RESET_ACTIVE) then
	       data_int <= (others => '0');
	       
	  -- On rising edge of clock, shift in data
	  elsif clock'event and clock = '1' then

	       -- Load data
	       if (data_ld = '1') then
		    data_int <= data_in;

	       -- If shift enable is high
	       elsif shift_en = '1' then

		    -- Shift the data
		    data_int <= data_int(6 downto 0) & shift_in;

	       end if;

	  end if;

     end process;
	shift_out <= data_int(7);     
	data_out <= data_int;

end DEFINITION;