mp3_post.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

n108_ff: pxa_tff_apar_p0 port map (n108_Q, n108_DIN, n108_C, n108_AP, 
               n108_AR); 
--------( n109 )-----------------------------------------------------------
n109_D      <= ((n111_Q_tF and not n108_Q_tF and not n107_Q_tF 
               and n110_Q_tF)
               or (not n111_Q_tF and n109_Q_tF and n110_Q_tF)
               or (n108_Q_tF and n109_Q_tF and n110_Q_tF)
               or (dld_rdy_COM_tF and downld_tIN)
               or (nstrobe_tIN and not nack_COM_tF)) after tLOGI2;
n109_mux: pxa_mux port map (n109_DIN, GND, GND, n109_D);
n109_C      <= (clock) after tGCK;
n109_AP     <= (GND) after tFIN;
n109_AR     <= not (rp_n_COM_tF) after tUDA;
n109_ff: pxa_dff_apar_p0 port map (n109_Q, n109_DIN, n109_C, n109_AP, 
               n109_AR); 
--------( n110 )-----------------------------------------------------------
n110_D      <= ((not n111_Q_tF and n110_Q_tF)
               or (n108_Q_tF and n110_Q_tF)
               or (not n107_Q_tF and n109_Q_tF and n110_Q_tF)
               or (n107_Q_tF and not n109_Q_tF and n110_Q_tF)
               or (not nstrobe_tIN and dld_rdy_COM_tF and downld_tIN)
               or (not downld_mode_dup_0_COM_tF and not gnd_pins_tIN 
               and downld_tIN)) after tLOGI2;
n110_mux: pxa_mux port map (n110_DIN, GND, GND, n110_D);
n110_C      <= (clock) after tGCK;
n110_AP     <= (GND) after tFIN;
n110_AR     <= not (rp_n_COM_tF) after tUDA;
n110_ff: pxa_dff_apar_p0 port map (n110_Q, n110_DIN, n110_C, n110_AP, 
               n110_AR); 
--------( n111 )-----------------------------------------------------------
n111_D      <= ((n107_Q_tF and n113_Q_tF and not n108_Q_tF and n112_Q_tF 
               and n114_Q_tF)
               or (not n107_Q_tF and not nx3738_COM_tF and n108_Q_tF)
               or (downld_mode_dup_0_COM_tF and n111_Q_tF 
               and not nx3738_COM_tF)
               or (n107_Q_tF and n111_Q_tF and N_PZ_4812_1_COM)
               or (n120_Q_tF and not n111_Q_tF and not nx3738_COM_tF 
               and not n108_Q_tF and N_PZ_4812_1_COM)) after tLOGI2;
n111_mux: pxa_mux port map (n111_DIN, GND, GND, n111_D);
n111_C      <= (clock) after tGCK;
n111_AP     <= (GND) after tFIN;
n111_AR     <= not (rp_n_COM_tF) after tUDA;
n111_ff: pxa_dff_apar_p0 port map (n111_Q, n111_DIN, n111_C, n111_AP, 
               n111_AR); 
--------( n112 )-----------------------------------------------------------
n112_T      <= not ((not n107_Q_tF and n113_Q_tF and n108_Q_tF 
               and n112_Q_tF and n114_Q_tF)
               or (n113_Q_tF and nx3738_COM_tF and n112_Q_tF and n114_Q_tF)
               or (nx3748_COM_tF and n107_Q_tF and not nx3738_COM_tF 
               and not n112_Q_tF and not n114_Q_tF)
               or (nx3748_COM_tF and not nx3738_COM_tF and not n108_Q_tF 
               and not n112_Q_tF and not n114_Q_tF)
               or (nx3748_COM_tF and n113_Q_tF and not n112_Q_tF 
               and not n114_Q_tF and N_PZ_4812_1_COM)
               or (nx3748_COM_tF and not n107_Q_tF and n113_Q_tF 
               and nx3738_COM_tF and n108_Q_tF and not n112_Q_tF 
               and N_PZ_4812_1_COM)
               or (not track_x_0_Q_tF and nx3748_COM_tF and n113_Q_tF 
               and nx3738_COM_tF and n108_Q_tF and not n112_Q_tF 
               and N_PZ_4812_1_COM)) after tLOGI2;
n112_mux: pxa_mux port map (n112_DIN, GND, GND, n112_T);
n112_C      <= (clock) after tGCK;
n112_AP     <= (GND) after tFIN;
n112_AR     <= not (rp_n_COM_tF) after tUDA;
n112_ff: pxa_tff_apar_p0 port map (n112_Q, n112_DIN, n112_C, n112_AP, 
               n112_AR); 
--------( n113 )-----------------------------------------------------------
n113_D      <= ((not n107_Q_tF and n113_Q_tF and n108_Q_tF and n112_Q_tF 
               and n114_Q_tF)
               or (not n113_Q_tF and n112_Q_tF and n114_Q_tF)
               or (n113_Q_tF and not n114_Q_tF)
               or (track_x_0_Q_tF and n107_Q_tF and n111_Q_tF 
               and n113_Q_tF and n108_Q_tF and not n112_Q_tF and n114_Q_tF)
               or (not n107_Q_tF and nx3738_COM_tF and block_tc_Q_tF 
               and not n112_Q_tF and not n114_Q_tF)
               or (n113_Q_tF and not nx3738_COM_tF and not n112_Q_tF)
               or (n107_Q_tF and n113_Q_tF and nx3738_COM_tF 
               and nx4220_1_COM)) after tLOGI2;
n113_mux: pxa_mux port map (n113_DIN, GND, GND, n113_D);
n113_C      <= (clock) after tGCK;
n113_AP     <= (GND) after tFIN;
n113_AR     <= not (rp_n_COM_tF) after tUDA;
n113_ff: pxa_dff_apar_p0 port map (n113_Q, n113_DIN, n113_C, n113_AP, 
               n113_AR); 
--------( n114 )-----------------------------------------------------------
n114_D      <= ((not n113_Q_tF and not n112_Q_tF and n114_Q_tF)
               or (n112_Q_tF and not n114_Q_tF)
               or (n113_Q_tF and n108_Q_tF and not n107_Q_tF and n112_Q_tF 
               and n114_Q_tF)
               or (track_x_0_Q_tF and n111_Q_tF and n113_Q_tF 
               and n108_Q_tF and n107_Q_tF and not n112_Q_tF and n114_Q_tF)
               or (nx3738_COM_tF and not n113_Q_tF and not n107_Q_tF 
               and block_tc_Q_tF and not n114_Q_tF)
               or (not nx3738_COM_tF and not n112_Q_tF and n114_Q_tF)
               or (nx3738_COM_tF and n113_Q_tF and n107_Q_tF and n114_Q_tF 
               and nx4220_COM)
               or (nx3720_COM_tF and n113_Q_tF and not n114_Q_tF)
               or (N_PZ_4858_COM_tF and not nx3738_COM_tF and n113_Q_tF 
               and N_PZ_4812_COM)) after tLOGI2;
n114_mux: pxa_mux port map (n114_DIN, GND, GND, n114_D);
n114_C      <= (clock) after tGCK;
n114_AP     <= (GND) after tFIN;
n114_AR     <= not (rp_n_COM_tF) after tUDA;
n114_ff: pxa_dff_apar_p0 port map (n114_Q, n114_DIN, n114_C, n114_AP, 
               n114_AR); 
--------( n115 )-----------------------------------------------------------
n115_T      <= ((not pup_tIN and n115_Q_tF)
               or (not on_off_sig_Q_tF and n115_Q_tF and n117_Q_tF)
               or (pup_tIN and not n116_Q_tF and not n115_Q_tF 
               and n117_Q_tF)) after tLOGI2;
n115_mux: pxa_mux port map (n115_DIN, GND, GND, n115_T);
n115_C      <= (clock) after tGCK;
n115_AP     <= (GND) after tFIN;
n115_AR     <= (GND) after tFIN;
n115_ff: pxa_tff_apar_p0 port map (n115_Q, n115_DIN, n115_C, n115_AP, 
               n115_AR); 
--------( n116 )-----------------------------------------------------------
n116_D      <= ((not on_off_sig_Q_tF and n115_Q_tF and n117_Q_tF)
               or (not pup_tIN and n115_Q_tF and n117_Q_tF)
               or (n116_Q_tF and not n115_Q_tF)) after tLOGI2;
n116_mux: pxa_mux port map (n116_DIN, GND, GND, n116_D);
n116_C      <= (clock) after tGCK;
n116_AP     <= (GND) after tFIN;
n116_AR     <= (GND) after tFIN;
n116_ff: pxa_dff_apar_p0 port map (n116_Q, n116_DIN, n116_C, n116_AP, 
               n116_AR); 
--------( n117 )-----------------------------------------------------------
n117_D      <= ((n116_Q_tF and not n115_Q_tF)
               or (pup_tIN and not n117_Q_tF)
               or (on_off_sig_Q_tF and pup_tIN and n115_Q_tF))
               after tLOGI2;
n117_mux: pxa_mux port map (n117_DIN, GND, GND, n117_D);
n117_C      <= (clock) after tGCK;
n117_AP     <= (GND) after tFIN;
n117_AR     <= (GND) after tFIN;
n117_ff: pxa_dff_apar_p0 port map (n117_Q, n117_DIN, n117_C, n117_AP, 
               n117_AR); 
--------( n120 )-----------------------------------------------------------
n120_D      <= ((n111_Q_tF and n113_Q_tF and n108_Q_tF and n120_Q_tF 
               and nx3738_COM_tF and n112_Q_tF and n114_Q_tF)
               or (n111_Q_tF and n113_Q_tF and not n120_Q_tF 
               and nx3738_COM_tF and n112_Q_tF and n114_Q_tF)
               or (not n111_Q_tF and n113_Q_tF and not n108_Q_tF 
               and n120_Q_tF and not nx3738_COM_tF and n112_Q_tF 
               and n114_Q_tF)) after tLOGI2;
n120_mux: pxa_mux port map (n120_DIN, GND, GND, n120_D);
n120_C      <= (clock) after tGCK;
n120_AP     <= (GND) after tFIN;
n120_AR     <= not (rp_n_COM_tF) after tUDA;
n120_ff: pxa_dff_apar_p0 port map (n120_Q, n120_DIN, n120_C, n120_AP, 
               n120_AR); 
--------( n121 )-----------------------------------------------------------
n121_D      <= ((n111_Q_tF and not n108_Q_tF and n107_Q_tF and n109_Q_tF 
               and n110_Q_tF)
               or (not nstrobe_tIN and not nack_COM_tF)) after tLOGI2;
n121_mux: pxa_mux port map (n121_DIN, GND, GND, n121_D);
n121_C      <= (clock) after tGCK;
n121_AP     <= (GND) after tFIN;
n121_AR     <= not (rp_n_COM_tF) after tUDA;
n121_ff: pxa_dff_apar_p0 port map (n121_Q, n121_DIN, n121_C, n121_AP, 
               n121_AR); 
--------( n122 )-----------------------------------------------------------
n122_D      <= ((not n123_Q_tF and not downld_mode_dup_0_COM_tF 
               and not stadr_out_COM_tF)
               or (n127_Q_tF and not n125_Q_tF and not n126_Q_tF 
               and not n122_Q_tF and not downld_mode_dup_0_COM_tF 
               and not n124_Q_tF and not stadr_out_COM_tF)) after tLOGI2;
n122_mux: pxa_mux port map (n122_DIN, GND, GND, n122_D);
n122_C      <= (clock) after tGCK;
n122_AP     <= (GND) after tFIN;
n122_AR     <= not (rp_n_COM_tF) after tUDA;
n122_ff: pxa_dff_apar_p0 port map (n122_Q, n122_DIN, n122_C, n122_AP, 
               n122_AR); 
--------( n123 )-----------------------------------------------------------
n123_D      <= not ((n127_Q_tF and not n125_Q_tF and not n126_Q_tF 
               and not n123_Q_tF and not n124_Q_tF 
               and not stadr_out_COM_tF)
               or (n127_Q_tF and not n125_Q_tF and not n126_Q_tF 
               and not n122_Q_tF and not n124_Q_tF 
               and not stadr_out_COM_tF)
               or (downld_mode_dup_0_COM_tF)
               or (rew_dup_0_COM_tF and stop_dup_0_COM_tF 
               and not n123_Q_tF and fwd_dup_0_COM_tF and stadr_out_COM_tF 
               and not play_Q_tF)
               or (rew_dup_0_COM_tF and stop_dup_0_COM_tF 
               and fwd_dup_0_COM_tF and not n122_Q_tF and stadr_out_COM_tF 
               and not play_Q_tF)) after tLOGI2;
n123_mux: pxa_mux port map (n123_DIN, GND, GND, n123_D);
n123_C      <= (clock) after tGCK;
n123_AP     <= (GND) after tFIN;
n123_AR     <= not (rp_n_COM_tF) after tUDA;
n123_ff: pxa_dff_apar_p0 port map (n123_Q, n123_DIN, n123_C, n123_AP, 
               n123_AR); 
--------( n124 )-----------------------------------------------------------
n124_T      <= not ((not adr_ld_u_dup_0_COM_tF and not n124_Q_tF)
               or (n127_Q_tF and not n126_Q_tF and adr_ld_u_dup_0_COM_tF 
               and n124_Q_tF and flash_done_dup_0_COM_tF)
               or (not n125_Q_tF and nx3590_COM_tF 
               and adr_ld_u_dup_0_COM_tF and n124_Q_tF)
               or (fwd_dup_0_COM_tF and not n127_Q_tF and not n125_Q_tF 
               and not n126_Q_tF and not nx3590_COM_tF 
               and stop_dup_0_COM_tF and not n124_Q_tF 
               and rew_dup_0_COM_tF)) after tLOGI2;
n124_mux: pxa_mux port map (n124_DIN, GND, GND, n124_T);
n124_C      <= (clock) after tGCK;
n124_AP     <= (GND) after tFIN;
n124_AR     <= not (rp_n_COM_tF) after tUDA;
n124_ff: pxa_tff_apar_p0 port map (n124_Q, n124_DIN, n124_C, n124_AP, 
               n124_AR); 
--------( n125 )-----------------------------------------------------------
n125_T      <= not ((track_x_0_Q_tF and not n125_Q_tF and n126_Q_tF 
               and adr_ld_u_dup_0_COM_tF and n124_Q_tF)
               or (n125_Q_tF and stadr_dec_dup_0_COM_tF and not n124_Q_tF)
               or (not track_x_0_Q_tF and not n125_Q_tF 
               and not track_x_2_Q_tF and n126_Q_tF 
               and adr_ld_u_dup_0_COM_tF and not track_x_1_Q_tF 
               and not track_x_3_Q_tF and not track_x_4_Q_tF 
               and stadr_dec_dup_0_COM_tF and n124_Q_tF)
               or (not n125_Q_tF and n126_Q_tF 
               and not stadr_dec_dup_0_COM_tF and not n124_Q_tF)
               or (not n127_Q_tF and not n125_Q_tF 
               and not stadr_dec_dup_0_COM_tF and not n124_Q_tF)
               or (track_x_0_Q_tF and not n127_Q_tF and not n125_Q_tF 
               and adr_ld_u_dup_0_COM_tF and not stadr_dec_dup_0_COM_tF))
               after tLOGI2;
n125_mux: pxa_mux port map (n125_DIN, GND, GND, n125_T);
n125_C      <= (clock) after tGCK;
n125_AP     <= (GND) after tFIN;
n125_AR     <= not (rp_n_COM_tF) after tUDA;
n125_ff: pxa_tff_apar_p0 port