mp3_post.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

---------------------------------------------------------------------------
-- XPLAOPT Version 3.32
-- VHDL Timing Model
-- Converted from JEDEC file
-- Created by Xilinx, Inc.
-- Design Name = mp3_cpld.blx
-- Device Name = XCR3256XL-7TQ144C
-- Feb 29 18:06:33 2000
---------------------------------------------------------------------------
package pxa_pkg is
    constant tLOGI1 : time := 2000 ps;
    constant tLOGI2 : time := 2500 ps;
    constant tLOGI3 : time := 6000 ps;
    constant tFIN  : time := 2200 ps;
    constant tIN   : time := 2500 ps;
    constant tF    : time := 2800 ps;
    constant tUDA  : time := 4000 ps;
    constant tGCK  : time := 1000 ps;
    constant tLDI  : time := 400 ps;
    constant toe_slew : time := 8500 ps;
    constant tbuf_slew : time := 6500 ps;
    constant tod      : time := 4500 ps;
    constant tap2q : time := 2000 ps;
    constant tar2q : time := 2000 ps;
    constant trd   : time := 1000 ps;
    constant tbuf  : time := 2500 ps;
    constant toe   : time := 4500 ps;
end pxa_pkg;
---------------------------------------------------------------------------
-- Components Defined Here
---------------------------------------------------------------------------
-- Output Buffer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_bufif2 is
	port (O: out std_logic; I, OE, SLEW : in std_logic);
end pxa_bufif2;
architecture behavioral of pxa_bufif2 is
signal OE_local, I_local : std_logic := '0';
begin
  OE_local <= OE after toe_slew when SLEW = '1' else OE after toe;
  I_local <= I after tbuf_slew when SLEW = '1' else I after tbuf;
  O <= I_local when OE_local = '1' else 'Z' after tod;
end behavioral;

-- Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_mux is
	port (O: out std_logic; S, A, B : in std_logic);
end pxa_mux;
architecture behavioral of pxa_mux is
begin
	O <= A when S = '1' else B;
end behavioral;

-- D Flip Flop with Asynchronous Preset/Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_dff_apar_p0 is
	port (Q : out std_logic; D, CLK, AP, AR : in std_logic);
end pxa_dff_apar_p0;
architecture behavioral of pxa_dff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
    elsif AP = '1' then
	   Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Preset/Reset
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_tff_apar_p0 is
	port (Q : out std_logic; T, CLK, AP, AR : in std_logic);
end pxa_tff_apar_p0;
architecture behavioral of pxa_tff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif AP = '1' then
      Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

---------------------------------------------------------------------------
-- Main VHDL Model 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity mp3_post is
    port(clock, downld, eod, fwd_button, gnd_pins, last_byte, mute_button,
         nstrobe, on_off_button, parallel_port_data_x_0,
         parallel_port_data_x_1, parallel_port_data_x_2,
         parallel_port_data_x_3, parallel_port_data_x_4,
         parallel_port_data_x_5, parallel_port_data_x_6,
         parallel_port_data_x_7, play_button, pup, rew_button, rtr,
         song_st, song_sts, stadr_sts, stop_button, vol_dec_button,
         vol_inc_button: in std_logic;
         downld_icon, error_icon, fwd_icon, mas_rst, play_icon, pr,
         rwd_icon, song_en, song_wr, stadr_en, stadr_wr, wsen
         : out std_logic;
         dld_rdy, nack, rp_n, scl, sda, song_adr_x_0, song_adr_x_1,
         song_adr_x_10, song_adr_x_11, song_adr_x_12, song_adr_x_13,
         song_adr_x_14, song_adr_x_15, song_adr_x_16, song_adr_x_17,
         song_adr_x_18, song_adr_x_19, song_adr_x_2, song_adr_x_20,
         song_adr_x_21, song_adr_x_22, song_adr_x_23, song_adr_x_24,
         song_adr_x_3, song_adr_x_4, song_adr_x_5, song_adr_x_6,
         song_adr_x_7, song_adr_x_8, song_adr_x_9, song_data_x_0,
         song_data_x_1, song_data_x_2, song_data_x_3, song_data_x_4,
         song_data_x_5, song_data_x_6, song_data_x_7, song_out, stadr_out,
         start_address_x_0, start_address_x_1, start_address_x_10,
         start_address_x_11, start_address_x_12, start_address_x_13,
         start_address_x_14, start_address_x_15, start_address_x_2,
         start_address_x_3, start_address_x_4, start_address_x_5,
         start_address_x_6, start_address_x_7, start_address_x_8,
         start_address_x_9, track_icon_x_0, track_icon_x_1, track_icon_x_2,
         track_icon_x_3, track_icon_x_4, track_icon_x_5, track_icon_x_6,
         track_x_0, track_x_1, track_x_2, track_x_3, track_x_4
         : inout std_logic
         );
end mp3_post;

architecture structure of mp3_post is

-------- Signal Declaration -----------------------------------------------
signal   N_PZ_4812_1_COM, N_PZ_4812_COM, N_PZ_4817_COM, N_PZ_4817_COM_tF,
         N_PZ_4858_COM, N_PZ_4858_COM_tF, N_PZ_4867_COM, N_PZ_4867_COM_tF,
         N_PZ_4885_COM, N_PZ_4885_COM_tF, N_PZ_4965_COM, N_PZ_4965_COM_tF,
         adr_ld_l_dup_0_COM, adr_ld_l_dup_0_COM_tF, adr_ld_u_dup_0_COM,
         adr_ld_u_dup_0_COM_tF, adr_up_dup_0_COM, adr_up_dup_0_COM_tF,
         block_tc_AP, block_tc_AR, block_tc_C, block_tc_DIN, block_tc_Q,
         block_tc_Q_tF, block_tc_T, detect_stop_AP, detect_stop_AR,
         detect_stop_C, detect_stop_D, detect_stop_DIN, detect_stop_Q,
         detect_stop_Q_tF, display_err_dup_0_COM, display_err_dup_0_COM_tF,
         dld_rdy_COM, dld_rdy_COM_tF, dld_rdy_OE, dnld_cnt_rst_AP,
         dnld_cnt_rst_AR, dnld_cnt_rst_C, dnld_cnt_rst_D, dnld_cnt_rst_DIN,
         dnld_cnt_rst_Q, dnld_cnt_rst_Q_tF, downld_icon_AP, downld_icon_AR,
         downld_icon_C, downld_icon_D, downld_icon_DIN, downld_icon_OE,
         downld_icon_Q, downld_mode_dup_0_COM, downld_mode_dup_0_COM_tF,
         downld_tIN, eod_tIN, eot_dup_0_COM, eot_dup_0_COM_tF,
         error_icon_AP, error_icon_AR, error_icon_C, error_icon_D,
         error_icon_DIN, error_icon_OE, error_icon_Q,
         flash_cntrl_end_flag_AP, flash_cntrl_end_flag_AR,
         flash_cntrl_end_flag_C, flash_cntrl_end_flag_D,
         flash_cntrl_end_flag_DIN, flash_cntrl_end_flag_Q,
         flash_cntrl_end_flag_Q_tF, flash_cntrl_lcomp_a_dup_0_COM,
         flash_cntrl_lcomp_a_dup_0_COM_tF, flash_cntrl_lcomp_b_dup_0_COM,
         flash_cntrl_lcomp_b_dup_0_COM_tF, flash_cntrl_lcomp_c_dup_0_COM,
         flash_cntrl_lcomp_c_dup_0_COM_tF, flash_cntrl_lcomp_d_dup_0_COM,
         flash_cntrl_lcomp_d_dup_0_COM_tF, flash_cntrl_ucomp_a_dup_0_COM,
         flash_cntrl_ucomp_a_dup_0_COM_tF, flash_cntrl_ucomp_b_dup_0_COM,
         flash_cntrl_ucomp_b_dup_0_COM_tF, flash_cntrl_ucomp_c_dup_0_COM,
         flash_cntrl_ucomp_c_dup_0_COM_tF, flash_done_dup_0_COM,
         flash_done_dup_0_COM_tF, fwd_button_tIN, fwd_dup_0_COM,
         fwd_dup_0_COM_tF, fwd_icon_AP, fwd_icon_AR, fwd_icon_C,
         fwd_icon_D, fwd_icon_DIN, fwd_icon_OE, fwd_icon_Q, gnd_pins_tIN,
         i2c_detect_start_AP, i2c_detect_start_AR, i2c_detect_start_C,
         i2c_detect_start_D, i2c_detect_start_DIN, i2c_detect_start_Q,
         i2c_detect_start_Q_tF, i2c_err_dup_0_COM, i2c_err_dup_0_COM_tF,
         i2c_gen_start_AP, i2c_gen_start_AR, i2c_gen_start_C,
         i2c_gen_start_D, i2c_gen_start_DIN, i2c_gen_start_Q,
         i2c_gen_start_Q_tF, i2c_gen_stop_AP, i2c_gen_stop_AR,
         i2c_gen_stop_C, i2c_gen_stop_D, i2c_gen_stop_DIN, i2c_gen_stop_Q,
         i2c_gen_stop_Q_tF, i2c_sda_out_reg_AP, i2c_sda_out_reg_AR,
         i2c_sda_out_reg_C, i2c_sda_out_reg_D, i2c_sda_out_reg_DIN,
         i2c_sda_out_reg_Q, i2c_sda_out_reg_Q_tF, i2c_shift_out_AP,
         i2c_shift_out_AR, i2c_shift_out_C, i2c_shift_out_D,
         i2c_shift_out_DIN, i2c_shift_out_Q, i2c_shift_out_Q_tF,
         i2c_shift_reg_en_AP, i2c_shift_reg_en_AR, i2c_shift_reg_en_C,
         i2c_shift_reg_en_D, i2c_shift_reg_en_DIN, i2c_shift_reg_en_Q,
         i2c_shift_reg_en_Q_tF, i2c_shift_reg_ld_AP, i2c_shift_reg_ld_AR,
         i2c_shift_reg_ld_C, i2c_shift_reg_ld_D, i2c_shift_reg_ld_DIN,
         i2c_shift_reg_ld_Q, i2c_shift_reg_ld_Q_tF, i2c_sm_stop_AP,
         i2c_sm_stop_AR, i2c_sm_stop_C, i2c_sm_stop_D, i2c_sm_stop_DIN,
         i2c_sm_stop_Q, i2c_sm_stop_Q_tF, i2c_start_d1_AP, i2c_start_d1_AR,
         i2c_start_d1_C, i2c_start_d1_D, i2c_start_d1_DIN, i2c_start_d1_Q,
         i2c_start_d1_Q_tF, i2c_stop_scl_reg_AP, i2c_stop_scl_reg_AR,
         i2c_stop_scl_reg_C, i2c_stop_scl_reg_D, i2c_stop_scl_reg_DIN,
         i2c_stop_scl_reg_Q, i2c_stop_scl_reg_Q_tF, last_byte_tIN,
         lower_comp_dup_0_COM, lower_comp_dup_0_COM_tF, mas_rst_AP,
         mas_rst_AR, mas_rst_C, mas_rst_D, mas_rst_DIN, mas_rst_OE,
         mas_rst_Q, mpeg_done_dup_0_COM, mpeg_done_dup_0_COM_tF,
         mpeg_eot_d1_AP, mpeg_eot_d1_AR, mpeg_eot_d1_C, mpeg_eot_d1_D,
         mpeg_eot_d1_DIN, mpeg_eot_d1_Q, mpeg_eot_d1_Q_tF, mute_button_tIN,
         mute_chg_AP, mute_chg_AR, mute_chg_C, mute_chg_D, mute_chg_DIN,
         mute_chg_Q, mute_chg_Q_tF, mute_stat_AP, mute_stat_AR,
         mute_stat_C, mute_stat_DIN, mute_stat_Q, mute_stat_Q_tF,
         mute_stat_T, n107_AP, n107_AR, n107_C, n107_DIN, n107_Q,
         n107_Q_tF, n107_T, n108_AP, n108_AR, n108_C, n108_DIN, n108_Q,
         n108_Q_tF, n108_T, n109_AP, n109_AR, n109_C, n109_D, n109_DIN,
         n109_Q, n109_Q_tF, n110_AP, n110_AR, n110_C, n110_D, n110_DIN,
         n110_Q, n110_Q_tF, n111_AP, n111_AR, n111_C, n111_D, n111_DIN,
         n111_Q, n111_Q_tF, n112_AP, n112_AR, n112_C, n112_DIN, n112_Q,
         n112_Q_tF, n112_T, n113_AP, n113_AR, n113_C, n113_D, n113_DIN,
         n113_Q, n113_Q_tF, n114_AP, n114_AR, n114_C, n114_D, n114_DIN,
         n114_Q, n114_Q_tF, n115_AP, n115_AR, n115_C, n115_DIN, n115_Q,
         n115_Q_tF, n115_T, n116_AP, n116_AR, n116_C, n116_D, n116_DIN,
         n116_Q, n116_Q_tF, n117_AP, n117_AR, n117_C, n117_D, n117_DIN,
         n117_Q, n117_Q_tF, n120_AP, n120_AR, n120_C, n120_D, n120_DIN,
         n120_Q, n120_Q_tF, n121_AP, n121_AR, n121_C, n121_D, n121_DIN,
         n121_Q, n121_Q_tF, n122_AP, n122_AR, n122_C, n122_D, n122_DIN,
         n122_Q, n122_Q_tF, n123_AP, n123_AR, n123_C, n123_D, n123_DIN,
         n123_Q, n123_Q_tF, n124_AP, n124_AR, n124_C, n124_DIN, n124_Q,
         n124_Q_tF, n124_T, n125_AP, n125_AR, n125_C, n125_DIN, n125_Q,
         n125_Q_tF, n125_T, n126_AP, n126_AR, n126_C, n126_DIN, n126_Q,
         n126_Q_tF, n126_T, n127_AP, n127_AR, n127_C, n127_DIN, n127_Q,
         n127_Q_tF, n127_T, n128_AP, n128_AR, n128_C, n128_D, n128_DIN,
         n128_Q, n128_Q_tF, n129_AP, n129_AR, n129_C, n129_D, n129_DIN,