dnld_interface.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		dnld_interface.vhd
--
-- Purpose: 	Description of PC parallel port interface with
--			song storage in flash memory during a download 
--			cycle.  This interface is used when the PC is 
--			downloading new MPEG songs to the MP3 portable player. 
--	
-- Created:		9-28-99 JLJ
-- Revised:		10-13-99 JLJ
-- Revised:		11-7-99 ALS
-- Revised:		11-14-99 ALS
-- Revised:		11-15-99 ALS
-- Revised:		11-26-99  ALS
-- **************************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity DNLD_INTERFACE is
    port(
        
        clock		: in STD_LOGIC;
        reset		: in STD_LOGIC;
        
        -- Parallel Port Interface signals
        dnld_mode		: in STD_LOGIC;			-- Active high, detect download mode 
        trs_rdy		: in STD_LOGIC;			-- Active high, data valid
        song_st		: in STD_LOGIC;			-- Active high, PC specifies start of song
        dnld_rdy		: out STD_LOGIC;			-- Active high, ready to transfer data
        wr_next		: out STD_LOGIC;			-- Active high, ready for next transfer
	  last_byte		: in	STD_LOGIC;			-- Active high, indicates the data byte
									-- is the last data byte of MP3 Data
                        
	  flash_cmd		: out STD_LOGIC_VECTOR(2 downto 0); -- Encodes commands to the Flash memories
        end_write_ers	: in STD_LOGIC;			-- Asserted if write or erase of either Flash is complete
	
	  dnld_cnt_rst	: out	STD_LOGIC			-- Asserted when download is complete to reset address
									-- counters
								

        );

end DNLD_INTERFACE;


architecture BEHAVIOURAL of DNLD_INTERFACE is

-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE 	: STD_LOGIC := '1';

-- Flash Commands
constant DO_NOTHING	: STD_LOGIC_VECTOR(2 downto 0) := "000";
constant WRITE_SONG	: STD_LOGIC_VECTOR(2 downto 0) := "100";
constant ERASE_SONG	: STD_LOGIC_VECTOR(2 downto 0) := "101";
constant ERASE_ST		: STD_LOGIC_VECTOR(2 downto 0) := "110";
constant WRITE_ST		: STD_LOGIC_VECTOR(2 downto 0) := "111";

-- ********************* SIGNAL DECLARATIONS ************************

-- Define states for download state machine
type STATE is (IDLE, F_ERASE, ST_ERASE, WAIT_ERASE,
			DNLD_READY, WRITE, WRITE_NEXT, WRITE_STADR, WRITE_WAIT);
signal prs_state, nxt_state : STATE;

signal dnld_cnt_rst_com	: STD_LOGIC;	-- combinatorial counter reset

begin

	-- Assert signal to write current address counter to starting address flash
	-- Either at start of each song or to store the end of data in the Song Flash
	-- Assert timing to write byte from PC to Song Flash
	-- Erase Song and StAdr flash before a download is ready to occur

	flash_cmd <= WRITE_ST when  (prs_state = WRITE_STADR) 
			else WRITE_SONG when (prs_state = WRITE)
			else ERASE_ST when (prs_state = ST_ERASE) 
			else ERASE_SONG when (prs_state = F_ERASE) 
			else DO_NOTHING;
	
	
	-- Assert wr_next to parallel port to identify ready for next byte of data
	wr_next <= '1' when (prs_state = WRITE_NEXT) else '0';

	-- Assert dnld_rdy to parallel port to identiy ready for download
	dnld_rdy <= '1' when (prs_state = DNLD_READY) else '0';




	-- ***************** Process: SEQUENTIAL ************************
	-- Purpose:  	Synchronize target state machine
	-- Components: 	none
    
    SEQUENTIAL: process (reset, clock)
    begin
        if reset = RESET_ACTIVE then	
            prs_state <= IDLE;
		dnld_cnt_rst <= RESET_ACTIVE;
            
        elsif clock'event and (clock = '1') then
            prs_state <= nxt_state;
		dnld_cnt_rst <= dnld_cnt_rst_com;
            
        end if;

    end process SEQUENTIAL;
    
    
    
    -- ******************** Process: DNLD_SM ************************
    -- Purpose: 	Target state machine to control transfer of data 
    --		in download mode between parallel port interface 
    --		flash control.  Handshakes with parallel port interface
    --		to determine timing for write of data to flash.  
    --		Starting Address Flash.  Controls erase of both flash
    --		memories before a download occurs.  The DNLD_SM state 
    --		machine manages the handshaking needed between both 
    --		components for transferring each byte of data.
    -- Components:	none
        
    DNLD_SM: process (prs_state, dnld_mode, end_write_ers, trs_rdy, song_st,
				last_byte)
    begin
    
    	 nxt_state <= prs_state;
	dnld_cnt_rst_com <= not(RESET_ACTIVE);
    	
        case prs_state is
        
        	------------------- IDLE State --------------------------
        	when IDLE =>
        		
        		-- Parallel port not connected in download mode
        		if dnld_mode = '1' then
        			nxt_state <= F_ERASE;
        			
        		end if;
        		
        	
        	------------------- F_ERASE State -----------------------
        	when F_ERASE =>
			-- This state erases the Song Flash  
        		-- Wait for erase complete signal from Flash control logic
			if end_write_ers = '1' then
				nxt_state <= WAIT_ERASE;
			end if;
		
		-------------------- WAIT_ERASE State -------------------
		when WAIT_ERASE =>
			-- This state wait for end_write_ers to negate
			if end_write_ers = '0' then
				nxt_state <= ST_ERASE;
			end if;

		-------------------- ST_ERASE State ----------------------
		when ST_ERASE =>
			-- This state erases the Starting Address Flash
			-- Wait for erase complete signal from the Flash control logic

        		if end_write_ers = '1' then
        			nxt_state <= DNLD_READY;
        		end if;
        		        	
        	
        	------------------- DNLD_READY State ----------------------
        	when DNLD_READY =>

			-- If download mode negates, download is complete so return to IDLE
			-- and reset counters
			if dnld_mode = '0' then
				nxt_state <= IDLE;
				dnld_cnt_rst_com <= RESET_ACTIVE;	
        		
        		-- Wait for trs_rdy signal from parallel port logic
           		elsif trs_rdy = '1' then
				if song_st = '1' or last_byte = '1' then
					-- if start of a song or last byte of MP3 data, 
					-- write starting address
					-- before writing data word because
					-- then the address is incremented
					nxt_state <= WRITE_STADR;
				else
        				nxt_state <= WRITE;
				end if;
        			
        		end if;
        		
        	
        	--------------------- WRITE State --------------------------
        	when WRITE =>
        
        		-- Wait for complete signal from flash logic
        			
        		if end_write_ers = '1' then
        			nxt_state <= WRITE_NEXT;
        			
        		end if;
        	
        	------------------- WRITE_NEXT State ------------------------
        	when WRITE_NEXT =>
			-- this state asserts the handshake signal to the parallel port
			-- logic       
        		nxt_state <= DNLD_READY;	        	        	
        	
        	------------------ WRITE_STADR State ---------------------
        	when WRITE_STADR =>
        	
        		if end_write_ers = '1' then
				nxt_state <= WRITE_WAIT;		
        		end if;	
		------------------- WRITE_WAIT ------------------------------
		when WRITE_WAIT =>
			-- this state waits for end_write to negate again before
			-- going to WRITE state
			if end_write_ers = '0' then
				nxt_state <= WRITE;
			end if;

		----------------------- DEFAULT -----------------------------
		when others =>
			nxt_state <= IDLE;	      
        	
        	        	
        end case;  
        
    end process DNLD_SM;
    


end BEHAVIOURAL;