updwncnt4.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		updwncnt4.vhd
--
-- Purpose: 	4-bit up-down counter to hold the volume level
--			This counter resets to the default volume level
--			of "1011". If up or down are asserted at the
--			same time, counter stays the same.
--	
-- Created:		10/27/99 ALS
--
-- Revised:	
--				
--
-- **************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


entity updwncnt4 is
	port(

		-- counter controls
	     	up       : in STD_LOGIC;                        -- Count up
	     	down	  : in std_logic;					-- Count down
	
		-- counter output
	     	qout     : out STD_LOGIC_VECTOR (3 downto 0);	-- count output

		-- clock and reset
		reset		: in std_logic;	-- active high reset
	     	clock       : in STD_LOGIC   -- Clock
	     		
	     );
		
end updwncnt4;



architecture DEFINITION of updwncnt4 is

-- ******************** CONSTANT DECLARATIONS **********************
constant RESET_ACTIVE : std_logic := '1';
constant DEFAULT_VOL : unsigned (3 downto 0) := "1011";

-- ******************** SIGNAL DECLARATIONS ***********************
signal q_int : UNSIGNED (3 downto 0);

begin

-- ******************** Count Process ***********************
-- This process defines the up/down counter.

count_proc:process(clock, reset)

     begin
          
          -- Clear output register
          if (reset = RESET_ACTIVE) then
	       q_int <= DEFAULT_VOL;
	       
	  -- On rising edge of clock count
	  elsif (clock'event) and clock = '1' then
		-- If both up and down are asserted, do nothing
		if up = '1' and down = '1' then
			q_int <= q_int;
		elsif up = '1' then
			-- increment
			q_int <= q_int + 1;
		elsif down = '1' then
			-- decrement
			q_int <= q_int - 1;
		else
			q_int <= q_int;
		end if;

	  end if;

     end process;

     qout <= STD_LOGIC_VECTOR(q_int);

end DEFINITION;