flash_cntr.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

			nxt_wrstate <= WRITE_CMD;  

 
        	------------------- WRITE_CMD State -----------------------
        	when WRITE_CMD =>
			
			-- this state negates WEN so that the data is written
			nxt_wrstate <= ENABLE_WRITE;
			case flash_cmd(1 downto 0) is
				when ERASE_SONG =>
					data_fl <= ERASE_COMMAND;
				when WRITE_SONG =>
					data_fl <= WRITE_COMMAND;
				when WRITE_ST =>
					data_stadr(7 downto 0) <= WRITE_COMMAND;
				when ERASE_ST =>
					data_stadr(7 downto 0) <= ERASE_COMMAND;
				when others =>
			end case;

		------------------- ENABLE_WRITE State ---------------------
		when ENABLE_WRITE =>
			-- this state assigns data and WEN is asserted in this state
			case flash_cmd(1 downto 0) is 
				when ERASE_SONG => 
					data_fl <= CONFIRM;
				when WRITE_SONG =>
					data_fl <= data;
				when ERASE_ST =>
					data_stadr(7 downto 0) <= CONFIRM;
				when WRITE_ST =>
					-- Write lower byte of Song Address
					if (track(0) = '1') then
						data_stadr <= song_adr(15 downto 0);
				
					else 
						-- Write upper byte of Song Address
						-- Record end of downloaded data in song flash 
						-- by writing upper bit of song_adr as '1'
						-- the value of signal LAST_BYTE becomes the MSB
						data_stadr <= last_byte & ZERO_BITS & song_adr(24 downto 16);
					end if;

				when others =>
			end case;

			nxt_wrstate <= WRITE_DATA;


        	------------------- WRITE_DATA State -----------------------
        	when WRITE_DATA =>
			-- this state negates WEN so that data is written
			-- wait for STS before moving to next state

				case flash_cmd(1 downto 0) is
					when ERASE_SONG =>
						if song_sts = FLASH_READY then
							-- for erase operation, next state is preset state
							-- so that the counter is incremented by a whole block
							data_fl <= CONFIRM;
							nxt_wrstate <= PRESET;
						end if;
					when WRITE_SONG =>
						if song_sts = FLASH_READY then
							data_fl <= data;
							nxt_wrstate <= INC_ADR;
						end if;
					when WRITE_ST => 
						if stadr_sts = FLASH_READY then
							-- Write lower byte of Song Address
							if (track(0) = '1') then
								data_stadr <= song_adr(15 downto 0);
				
							else 
								-- Write upper byte of Song Address
								-- Record end of downloaded data in song flash 
								-- by writing upper bit of song_adr as '1'
								-- the value of signal LAST_BYTE becomes the MSB
								data_stadr <= last_byte & ZERO_BITS & song_adr(24 downto 16);
							end if;
							nxt_wrstate <= INC_ADR;
						end if;  
					when ERASE_ST =>
 						if stadr_sts = FLASH_READY then
							data_stadr(7 downto 0) <= CONFIRM;
							-- only need to erase one block, so no need to preset
							-- simply go to increment address state
							nxt_wrstate <= INC_ADR;	
						end if;
					when others =>
		       	
				end case;		
              
		-------------------- PRESET State -----------------------
		when PRESET =>
			-- this state asserts the PRESET_LOWER signal to the 
			-- song flash address counter if this is an erase
			nxt_wrstate <= INC_ADR;
	
        	-------------------- INC_ADR State ------------------------
        	when INC_ADR =>
		
			case flash_cmd(1 downto 0) is
				when WRITE_SONG =>
					-- Done writing data byte to song flash
					nxt_wrstate <= DONE;
				when ERASE_ST =>
					-- Done writing data byte to song flash
					nxt_wrstate <= DONE;
				when ERASE_SONG =>
					-- check terminal count of address counter
					-- in IDLE state
					nxt_wrstate <= IDLE;

				when WRITE_ST =>
					-- Check if lower byte still needs to be written
					if (track(0) = '0') then
						-- lower byte needs to be written - go to IDLE
						-- state to allow address to stabilize
						nxt_wrstate <= IDLE;
					else
						-- both bytes have been written, go to DONE state
						nxt_wrstate <= DONE;
					end if;
				when others =>

			end case;

	
        	-------------------- DONE State ------------------------
        	when DONE =>
			-- this state asserts the FLASH_DONE signal
			-- wait for commands to be negated before going to IDLE			
        		if flash_cmd(2) = '0' then
        			nxt_wrstate <= IDLE;	
        		end if;       			
 
        	    	
        end case;  
        
    end process WRITE_ERASE;
   


	    
    -- ***************** Process: READ_SONG_SM ************************
    -- Purpose:	This process contains the combinatorial portion 
    --		of the state machine.  This state machine asserts 
    --		the signals to read data from the Song flash memory 
    --		and increments the address counter.
    -- Components:  none
        
    READ_SONG_SM: process (rd_state, read, wakeup, downld_mode)
    begin
	
		next_rd_state <= rd_state;

		case rd_state is 

			-- ******************** IDLE State ********************
			when IDLE =>

				-- Leave this state when the WAKEUP signal is asserted
				-- and a download operation is not occuring	
				if (wakeup = '1') then
					next_rd_state <= ENABLE_READ;
				end if;
			
			-- ******************** ENABLE_READ State ***************
			when ENABLE_READ =>

				-- If a download occurs, the state machine goes back to the 
				-- IDLE state so that the WRITE and ERASE state machines
				-- can control the flash				
				-- when READ asserts, move to the next state
				if read = '1' then
					next_rd_state <= READ_DATA;
				end if;

			-- ******************** READ_DATA State ******************
			when READ_DATA =>

				-- This state is used as a holding state where the flash
				-- data is held constant until the READ signal negates

				-- If a download occurs, the state machine goes back to the 
				-- IDLE state so that the WRITE and ERASE state machines
				-- can control the flash			
				if read = '0' then
					next_rd_state <= INC_ADDR;
				end if;				
		
			-- ******************** INC_ADDR State ******************
			when INC_ADDR =>
				-- This state increments the address counter for the flash
				-- the CE and OEN signals to the Flash are kept active so
				-- that the data will be available as soon as possible

				-- If a download occurs, the state machine goes back to the 
				-- IDLE state so that the WRITE and ERASE state machines
				-- can control the flash, otherwise, keep the flash memories
				-- enabled for a read operation
				next_rd_state <= ENABLE_READ;
			
			-- ********************* DEFAULT **************************
			when others =>
				next_rd_state <= IDLE;	
	
		end case;

	end process READ_SONG_SM;




    -- ***************** Process: READ_STADR_SM ************************
    -- Purpose:	This process contains the combinatorial portion 
    --		of the state machine.  This state machine asserts 
    --		the signals to read data from the Starting Address
    --		flash memory.
    -- Components:  none
        
    READ_STADR_SM: process (rd_stadr_state, read_stadr, downld_mode, rew, fwd, stop,
				    play)
    begin
	
		nxt_stadr_state <= rd_stadr_state;
		
		case rd_stadr_state is 

			-- ******************** IDLE State ********************
			when IDLE =>

				-- Leave this state when rewind, fast forward
				-- or stop opertation	
				if ((rew = '1') or (fwd = '1') or (stop = '1') or (play = '1')) then
					nxt_stadr_state <= ENABLE_READ;
				end if;
			
			-- ******************** ENABLE_READ State ***************
			when ENABLE_READ =>

				-- Enable Starting Address Flash to read
				if read_stadr = '1' then
					nxt_stadr_state <= READ_DATA;
				end if;

			-- ******************** READ_DATA State ******************
			when READ_DATA =>

				-- This state is used as a holding state where the flash
				-- data is held constant until the READ_STADR signal negates

				-- If a download occurs, the state machine goes back to the 
				-- IDLE state so that the WRITE and ERASE state machines			
				if read_stadr = '0' then
					nxt_stadr_state <= INC_ADDR;
				end if;				
		
			-- ******************** INC_ADDR State ******************
			when INC_ADDR =>
				-- This state increments the stadr address counter for the 
				-- starting address flash.

				-- If a download occurs, the state machine goes back to the 
				-- IDLE state so that the WRITE and ERASE state machines
				-- can control the flash, otherwise, keep the flash memories
				-- enabled for a read operation
				nxt_stadr_state <= ENABLE_READ;
			
			-- ********************* DEFAULT **************************
			when others =>
				nxt_stadr_state <= IDLE;	
	
		end case;

	end process READ_STADR_SM;


    -- ***************** Process: CMP_ADDR_SM ************************
    -- Purpose:	This process contains the combinatorial portion 
    --		of the state machine.  This state machine asserts 
    --		the signals to read data from the Song flash memory 
    --		and increments the address counter.
    -- Components:  none
        
    CMP_ADDR_SM: process (prs_cmp_state, play, read, song_end, track, upper_comp, lower_comp,
				  end_flag, song_start)
    begin
	
		song_end_com <= song_end;
		song_start_com <= song_start;
		nxt_cmp_state <= prs_cmp_state;
		saf_inc <= '0';

		case prs_cmp_state is 

			-- ******************** IDLE State ********************
			when IDLE =>
				song_end_com <= '0';
				song_start_com <= '0';

				-- Leave this state when the read and play operation
				-- are asserted	
				if (play = '1') and (read = '1') then
					nxt_cmp_state <= READ_ST;
					
				end if;
			
			-- ******************** READ_ST State ***************
			when READ_ST =>
				
				
				if (track(0) = '0') then
					
					-- Checking upper byte of song address
					if upper_comp = '1' then
						nxt_cmp_state <= MATCH;
						saf_inc <= '1';
					
					-- Else no match, return to beginning
					else
						nxt_cmp_state <= IDLE;

					end if;
				
				else
					-- track(0) = 1, checking lower byte of data

					-- Check lower byte of song address
					if lower_comp = '1' then

						if (read = '0') then
							if (end_flag = '1') then
								song_end_com <= '1';
							else
								song_start_com <= '1';

							end if;

							nxt_cmp_state <= START_END;
						end if;

					-- Else no match, return to beginning
					else
						nxt_cmp_state <= IDLE;
					end if;

				end if;
			


			-- ******************** MATCH State ******************
			when MATCH =>

				-- Increment address counter and match count
				nxt_cmp_state <= READ_ST;				

			-- ******************** START_END State ******************
			when START_END =>		

				-- Reinitialize match counter

				saf_inc <= '1';
				nxt_cmp_state <= IDLE;
				
			
			-- ********************* DEFAULT **************************
			when others =>
				nxt_cmp_state <= IDLE;	
	
		end case;

	end process CMP_ADDR_SM;




end BEHAVIOURAL;