📄 flash_cntr.vhd
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-- **************************************************************
-- File: flash_cntr.vhd
--
-- Purpose: Implements write/erase and read commands on flash
-- modules. Creates the necessary enable lines
-- to write, erase, or read both the starting address
-- and song data flash blocks.
--
-- Created: 10-13-99 JLJ
-- Revised: 10-27-99 JLJ
-- Revised: 11-2-99 JLJ
-- Revised: 11-4-99 ALS
-- Revised: 11-5-99 ALS
-- Revised: 11-7-99 ALS
-- Revised: 11-9-99 JLJ
-- Revised: 11-12-99 ALS & JLJ
-- Revised: 11-14-99 ALS
-- Revised: 11-16-99 ALS
-- Revised: 11-26-99 ALS
-- Revised: 11-28-99 ALS
-- Revised: 12-3-99 ALS
-- Revised: 12-6-99 ALS
-- Revised: 02-23-00 ALS
-- **************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity FLASH_CNTR is
port(
clock : in STD_LOGIC;
reset : in STD_LOGIC;
-- Download Control Signals
downld_mode : in STD_LOGIC; -- Active high in download mode
flash_cmd : in STD_LOGIC_VECTOR(2 downto 0); -- contains flash operation
end_write_ers : out STD_LOGIC; -- Asserted if write or erase function is complete
data : in STD_LOGIC_VECTOR(7 downto 0); -- Data byte from PC in download
flash_data : out STD_LOGIC_VECTOR(7 downto 0); -- Data byte to write to flash
last_byte : in STD_LOGIC; -- Asserted by download software when the
-- current data is the last byte of MP3 data
-- Operational Control Signals
play : in STD_LOGIC; -- Asserted during play mode
wakeup : in STD_LOGIC; -- Asserted to wakeup flashes for read operation
read : in STD_LOGIC; -- Asserted to read byte of data from Song Flash:
-- While read = 1, the data should be held constant
-- When read = 0, the address can be incremented so that
-- the next word is available
read_stadr : in STD_LOGIC; -- Asserted to read from Starting Address Flash:
-- 16 bit wide read when read_stadr = 1
rew : in STD_LOGIC; -- Asserted high for rewind operation
fwd : in STD_LOGIC; -- Asserted high for fast forward opertion
stop : in STD_LOGIC; -- Asserted high for stop opertion
-- Song Flash Control Signals
song_en : out STD_LOGIC; -- Asserted high to enable song flash
song_out : out STD_LOGIC; -- Asserted low for output enable of song flash
song_wr : out STD_LOGIC; -- Asserted low for write enable of song flash
song_sts : in STD_LOGIC; -- READY/BUSY signal from song flash
rp_n : out STD_LOGIC; -- Active low reset to both flash modules
-- Starting Address Flash Control Signals
stadr_en : out STD_LOGIC; -- Asserted high to enable stadr flash
stadr_out : out STD_LOGIC; -- Asserted low for output enable of stadr flash
stadr_wr : out STD_LOGIC; -- Asserted low for write enable of stadr flash
stadr_sts : in STD_LOGIC; -- READY/BUSY signal from stadr flash
-- Change starting address counter
stadr_inc : in STD_LOGIC; -- Asserted on fast forward operation
stadr_dec : in STD_LOGIC; -- Asserted on rewind operation
dnld_cnt_rst : in STD_LOGIC; -- Asserted when download operation is finished to
-- reset address counters
cmd_song_end : in STD_LOGIC; -- Asserted when command state machine finds end
-- of song data
end_flag_com : inout STD_LOGIC; -- Asserted when upper address bit is end data flag
-- Test Outputs
adr_up : inout STD_LOGIC;
preset_lower : inout STD_LOGIC;
st_inc : inout STD_LOGIC;
st_dec : inout STD_LOGIC;
st_rst : inout STD_LOGIC;
upper_comp : inout STD_LOGIC;
lower_comp : inout STD_LOGIC;
--ucomp : inout std_logic_vector(2 downto 0);
--lcomp : inout std_logic_vector(3 downto 0);
block_tc : in std_logic;
-- Address and data vectors for song and starting address flash modules
song_adr : in STD_LOGIC_VECTOR(24 downto 0); -- Song Flash Address
track : in STD_LOGIC_VECTOR(4 downto 0); -- Stadr Flash Address
stadr_data : inout STD_LOGIC_VECTOR(15 downto 0); -- Stadr Data (=>Song Flash Address)
song_end : inout STD_LOGIC; -- Asserted from compare address state machine when
-- end of song data has been reached and track number
-- needs to be set back to 1st song address
song_start : inout STD_LOGIC -- Asserted at detect of new song from compare
-- address state machine
);
end FLASH_CNTR;
architecture BEHAVIOURAL of FLASH_CNTR is
-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE : STD_LOGIC := '1';
constant ZERO_BITS : STD_LOGIC_VECTOR(5 downto 0) := "000000";
constant SIXTEEN_ONES : STD_LOGIC_VECTOR(15 downto 0) := (others => '1');
constant NINE_ONES : STD_LOGIC_VECTOR(8 downto 0) := (others => '1');
-- Commands to the Flash Memory Modules
constant WRITE_COMMAND : std_logic_vector(7 downto 0) := "01000000"; -- 40\h
constant ERASE_COMMAND : std_logic_vector(7 downto 0) := "00100000"; -- 20\h
constant CONFIRM : std_logic_vector(7 downto 0) := "11010000"; -- D0\h
-- Flash Operations
constant WRITE_SONG : std_logic_vector(1 downto 0) := "00";
constant ERASE_SONG : std_logic_vector(1 downto 0) := "01";
constant ERASE_ST : std_logic_vector(1 downto 0) := "10";
constant WRITE_ST : std_logic_vector(1 downto 0) := "11";
-- Flash status
constant FLASH_READY : std_logic := '1';
-- ********************* SIGNAL DECLARATIONS ************************
-- Define state type for write/erase and read state machine
type WR_STATE is (IDLE, ENABLE_CMD, WRITE_CMD, ENABLE_WRITE, WRITE_DATA, PRESET, INC_ADR, DONE);
type READ_STATE is (IDLE, ENABLE_READ, READ_DATA, INC_ADDR);
-- Define state type for compare address state machine
type CMP_STATE is (IDLE, READ_ST, MATCH, START_END);
-- States for write/erase and read state machine
signal prs_wrstate, nxt_wrstate : WR_STATE;
signal rd_state, next_rd_state : READ_STATE; -- Read Song flash state machine
signal rd_stadr_state, nxt_stadr_state : READ_STATE; -- Read Starting Address flash sm
signal prs_cmp_state, nxt_cmp_state : CMP_STATE; -- Compare addr sm state signals
signal end_flag : STD_LOGIC; -- indicates that upper address of the
-- end of flash data has been reached
-- Song Address Counter Interface Signals
signal saf_inc : std_logic;
-- Song Flash signals
signal data_fl : std_logic_vector(7 downto 0); -- data to be written to the flash
signal data_oe : std_logic; -- enables data from the write state machine to
-- be driven to the flash
-- Starting Address Flash Signals
signal data_stadr : std_logic_vector(15 downto 0); -- data to be written to the starting address flash
signal stdata_oe : std_logic; -- enables data from the write state machine to be driven to
-- the flash
signal start_address : std_logic_vector(15 downto 0); -- data input from the flash
-- Song end, song_start combinatorial signals
signal song_end_com : std_logic;
signal song_start_com : std_logic;
-- Comparator signals
signal ucomp_a, ucomp_b, ucomp_c : std_logic;
signal lcomp_a, lcomp_b, lcomp_c, lcomp_d : std_logic;
begin
-- Song Flash Control Signals
rp_n <= not(reset); -- reset to both song flash and starting address flash is opposite sense
-- from reset
song_en <= '1' when ((flash_cmd(2) = '1') and (flash_cmd(1) = '0') and (prs_wrstate /= IDLE)) or
((rd_state = ENABLE_READ) or (rd_state = READ_DATA))
else '0';
song_wr <= '0' when ((flash_cmd(1)= '0') and
(prs_wrstate = ENABLE_WRITE or prs_wrstate = ENABLE_CMD))
else '1';
song_out <= '1' when (rd_state = IDLE) else '0';
-- Starting Address Flash enable/output signals
stadr_en <= '1' when ((flash_cmd(1) = '1') and (prs_wrstate /= IDLE)) or
((rd_stadr_state = ENABLE_READ) or (rd_stadr_state = READ_DATA))
else '0';
stadr_wr <= '0' when ((flash_cmd(1) = '1')
and ((prs_wrstate = ENABLE_WRITE) or (prs_wrstate = ENABLE_CMD)))
else '1';
stadr_out <= '1' when (rd_stadr_state = IDLE) else '0';
-- Assert end flag in done state of write/erase state machine
end_write_ers <= '1' when prs_wrstate = DONE
else '0';
-- Song Address Counter signals
adr_up <= '1' when ((flash_cmd(1) = '0') and (prs_wrstate = INC_ADR)) or
(rd_state = INC_ADDR) else '0';
preset_lower <= '1' when (prs_wrstate = PRESET)
else '0';
-- Starting Address Counters signals
st_inc <= '1' when ((flash_cmd(1 downto 0) = WRITE_ST) and (prs_wrstate = INC_ADR)) or
(rd_stadr_state = INC_ADDR) or
(saf_inc = '1') or
(stadr_inc = '1') else '0';
st_rst <= RESET_ACTIVE when ((reset = RESET_ACTIVE) or
-- ((downld_mode = '0') and (prs_wrstate = DONE)) or
(dnld_cnt_rst = RESET_ACTIVE) or
(song_end = '1') or (cmd_song_end = '1')) else (not RESET_ACTIVE);
st_dec <= '1' when stadr_dec = '1' else '0';
-- Flash data output enable
-- assert song flash OE when write or erase to this flash (flash_cmd(1) = '0')
-- and flash operations are active (flash_cmd(2) = '1')
data_oe <= '1' when flash_cmd(2 downto 1) = "10"
else '0';
flash_data <= data_fl when data_oe = '1'
else (others => 'Z');
-- assert starting address flash OE when write or erase to this flash (flash_cmd(1)=1)
-- and flash operations are active (flash_cmd(2) = '1')
stdata_oe <= '1' when flash_cmd(2 downto 1) = "11"
else '0';
stadr_data <= data_stadr when stdata_oe = '1'
else (others => 'Z');
start_address <= stadr_data;
-- Address Compare Signals
ucomp_a <= '1' when (song_adr(18 downto 16) = start_address(2 downto 0))
else '0';
ucomp_b <= '1' when (song_adr(21 downto 19) = start_address(5 downto 3))
else '0';
ucomp_c <= '1' when (song_adr(24 downto 22) = start_address(8 downto 6))
else '0';
lcomp_a <= '1' when (song_adr(3 downto 0) = start_address(3 downto 0))
else '0';
lcomp_b <= '1' when (song_adr(7 downto 4) = start_address(7 downto 4))
else '0';
lcomp_c <= '1' when (song_adr(11 downto 8) = start_address(11 downto 8))
else '0';
lcomp_d <= '1' when (song_adr(15 downto 12) = start_address(15 downto 12))
else '0';
upper_comp <= '1' when ucomp_a = '1' and ucomp_b = '1' and ucomp_c = '1'
else '0';
lower_comp <= '1' when lcomp_a = '1' and lcomp_b = '1' and lcomp_c = '1' and lcomp_d = '1'
else '0';
end_flag_com <= '1' when (start_address(15) = '1')
else '0';
-- ***************** Process: SEQUENTIAL ************************
-- Purpose: Synchronize write_erase, read, and compare address
-- target state machines.
-- Components: none
SEQUENTIAL: process (reset, clock)
begin
if reset = RESET_ACTIVE then
prs_wrstate <= IDLE;
rd_state <= IDLE;
rd_stadr_state <= IDLE;
prs_cmp_state <= IDLE;
song_end <= '0';
song_start <= '0';
end_flag <= '0';
elsif clock'event and (clock = '1') then
prs_wrstate <= nxt_wrstate;
if downld_mode = '0' then
rd_state <= next_rd_state;
rd_stadr_state <= nxt_stadr_state;
else
rd_state <= IDLE;
rd_stadr_state <= IDLE;
end if;
prs_cmp_state <= nxt_cmp_state;
song_end <= song_end_com;
song_start <= song_start_com;
if play = '0' then
end_flag <= '0';
elsif track(0) = '0' then
end_flag <= end_flag_com;
else
end_flag <= end_flag;
end if;
end if;
end process SEQUENTIAL;
-- ***************** Process: WRITE_ERASE ************************
-- Purpose: Manage the control signals to write and erase
-- on both the song and starting address flash modules. This
-- state machine controls the chip select/functions for each
-- flash module. Checks the status register on each module and
-- asserts the appropriate error flag. Manages size differences
-- between data byte and size of data storage.
-- Components: cnt6 : 6-bit track number counter
-- cnt25 : 25-bit song address counter
WRITE_ERASE: process (prs_wrstate, flash_cmd, track(0), data, song_adr, last_byte,
downld_mode, song_sts, stadr_sts, block_tc)
begin
nxt_wrstate <= prs_wrstate;
data_fl <= (others => '0');
data_stadr <= (others => '0');
case prs_wrstate is
------------------- IDLE State --------------------------
when IDLE =>
-- Check MSB of Flash Command to see if a flash operation
-- is required, then decode the command
if flash_cmd(2) = '1' then
case flash_cmd(1 downto 0) is
when ERASE_SONG =>
-- if erase then check terminal count
if block_tc = '1' then
nxt_wrstate <= DONE;
else
nxt_wrstate <= ENABLE_CMD;
end if;
when WRITE_SONG =>
nxt_wrstate <= ENABLE_CMD;
when WRITE_ST =>
nxt_wrstate <= ENABLE_CMD;
when ERASE_ST =>
nxt_wrstate <= ENABLE_CMD;
when others =>
end case;
end if;
--------------------- ENABLE_CMD State ------------------------
when ENABLE_CMD =>
-- Setup write and erase operations on both flash modules
-- WEN is asserted in this state
case flash_cmd(1 downto 0) is
when ERASE_SONG =>
data_fl <= ERASE_COMMAND;
when WRITE_SONG =>
data_fl <= WRITE_COMMAND;
when WRITE_ST =>
data_stadr(7 downto 0) <= WRITE_COMMAND;
when ERASE_ST =>
data_stadr(7 downto 0) <= ERASE_COMMAND;
when others =>
end case;
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