play_modes.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		play_modes.vhd
--
-- Purpose: 	This file implements the Play Modes section of the
--			user interface.  This module outputs a vector that
--			specifies the play status of the mp3 player. The input
--			signals are evaluated on the rising edge of the input 
--			signal and the clock signal.
--
--			Inputs: play,pause,stop,rwd,fwd,flash_done,reset,clock
--			Outputs:play_stat[2:0]
--
--			play_stat[2:0]|  play mode
--			--------------|-------------
--				000	  |  play
--				001	  |  pause
--				010	  |  stop
--				011	  |  fwd
--				100	  |  rwd
--				101	  |  noop
--				110	  |  noop
--				111	  |  noop
--
-- Created:		10/15/99	CLH
-- Revised:		10/21/99	ALS
-- Revised:		11/5/99 	ALS
-- Revised: 	11/14/99 ALS
--			Changed meaning of PLAY_STAT:
--
--			play_stat[2:0]|  play mode
--			--------------|-------------
--				000	  |  play
--				001	  |  rewind
--				010	  |  stop
--				011	  |  fwd
--				100	  |  noop
--				101	  |  noop
--				110	  |  noop
--				111	  |  noop
--			
--			Now PLAY_STAT[2] indicates no-op or operation
-- 
-- Revised:		02/23/00 	ALS
-- **************************************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity play_modes is
  
  port(
	clock 	: in STD_LOGIC;
	reset		: in STD_LOGIC;
	
	-- input signals from User Buttons
	play		: in STD_LOGIC;
	stop		: in STD_LOGIC;
	rwd		: in STD_LOGIC;
	fwd		: in STD_LOGIC;

	-- signal from Flash Control Logic indicating that 
	-- the flash is done with the operation
	flash_done	: in STD_LOGIC;

	-- output signals
	play_stat	: out STD_LOGIC_VECTOR(2 downto 0)
	);
end play_modes;

architecture behave of play_modes is

constant RESET_ACTIVE	: STD_LOGIC := '1';

constant REG_DELAY	: time := 3 nS;

-- PLAY_STAT decode
constant PLAY_CODE	:	std_logic_vector(2 downto 0) := "000"; -- play_stat code for play
constant REW_CODE		: 	std_logic_vector(2 downto 0) := "001"; -- play_stat code for pause
constant STOP_CODE	:	std_logic_vector(2 downto 0) := "010"; -- play_stat code for stop
constant FWD_CODE		: 	std_logic_vector(2 downto 0) := "011"; -- play_stat code for fast forward
constant DO_NOTHING	:	std_logic_vector(2 downto 0) := "111"; -- one of the codes for nothing

	-- Define states for play status
	type STATE is (ST_IDLE, ST_PLAY, ST_STOP, ST_FWD, ST_RWD);	
	signal curr_state, nxt_state : STATE;

	-- define variables for process
	signal curr_mode:	STD_LOGIC;	--defines previous play mode when fwd/rwd pushed. 
						-- 1 = play; 0 = stop
	signal curr_mode_com: STD_LOGIC;	-- combinatorial variable of curr_mode
	signal play_reg: STD_LOGIC;		-- registered variables for inputs; used in rising edge detection
	signal stop_reg: STD_LOGIC;
	signal fwd_reg: STD_LOGIC;
	signal rwd_reg: STD_LOGIC;
	signal play_re: STD_LOGIC;		-- used in rising edge detection
	signal stop_re: STD_LOGIC;
	signal fwd_re: STD_LOGIC;
	signal rwd_re: STD_LOGIC;
	begin

	-- ************* Process: INPUT_REG **************
	-- Purpose: provide registered value that will be
	-- used in the PLAY_SM process to determine if input
	-- signal is a rising edge
	-- Components: None

	INPUT_REG: process(reset, clock)
	begin
		if reset =  RESET_ACTIVE then	
			play_reg <= '0' ;
			stop_reg <= '0' ;
			fwd_reg <= '0' ;
			rwd_reg <= '0' ;
		elsif clock'event and (clock = '1') then
			play_reg <= play ;
			stop_reg <= stop ;
			fwd_reg <= fwd ;
			rwd_reg <= rwd ;
		end if;		

	end process INPUT_REG;

-- determine rising edges
play_re <= '1' when play = '1' and play_reg = '0'
		else '0';
stop_re <= '1' when stop = '1' and stop_reg = '0'
		else '0';
rwd_re <= '1' when rwd = '1' and rwd_reg = '0'
		else '0';
fwd_re <= '1' when fwd = '1' and fwd_reg = '0'
		else '0';

	-- ************* Process: SEQUENTIAL **************
	-- Purpose: Synchronize target state machine
	-- Components: None

	SEQUENTIAL: process(reset, clock)
	begin
		if reset =  RESET_ACTIVE then
			curr_state <= ST_IDLE ;
			curr_mode <= '0' ;	
		elsif clock'event and (clock = '1') then
			curr_state <= nxt_state ;
			curr_mode <= curr_mode_com ;
		end if;
	end process SEQUENTIAL;



	-- ************* Process: PLAY_SM **************
	-- Purpose: Target state machine to define play_status
	-- Components: None


	PLAY_SM: process(curr_state, play_re, stop_re, rwd_re, fwd_re, flash_done,
			     curr_mode)
	begin

	curr_mode_com <= curr_mode;	-- reset curr_mode_com
	nxt_state <= curr_state;	-- reset state variable

	case curr_state is

		------------- ST_IDLE State --------------
		when ST_IDLE =>
		curr_mode_com <= '0';
		play_stat <= DO_NOTHING;
		if play_re = '1' then
			nxt_state <= ST_PLAY;
		elsif fwd_re = '1' then
			nxt_state <= ST_FWD;
		elsif rwd_re = '1' then
			nxt_state <= ST_RWD;
		end if;


		------------- ST_PLAY State --------------
		when ST_PLAY =>
		play_stat <= PLAY_CODE;
		curr_mode_com <= '1';

		if stop_re = '1' then
			nxt_state <= ST_STOP;
		elsif fwd_re = '1' then
			nxt_state <= ST_FWD;
		elsif rwd_re = '1' then
			nxt_state <= ST_RWD;
		end if;

		------------- ST_STOP State --------------
		when ST_STOP =>		
		
		play_stat <= STOP_CODE;
		curr_mode_com <= '0';
		
		-- Check that Flash Control Logic has completed
		-- operation before checking for next state
		if flash_done = '1' then

			if play_re = '1' then
				nxt_state <= ST_play;
			elsif fwd_re = '1' then
				nxt_state <= ST_FWD;
			elsif rwd_re = '1' then
				nxt_state <= ST_RWD;
			else
				nxt_state <= ST_IDLE;
			end if;
		end if;
		
		------------- ST_FWD State --------------
		when ST_FWD =>

		play_stat <= FWD_CODE;
		if flash_done = '1' then		-- check to see if flash has completed
			if curr_mode = '1' then		-- check current mode (play or stop)
				nxt_state <= ST_play;	-- return to correct state		
			else
				nxt_state <= ST_IDLE;
			end if;

		end if;

		------------- ST_RWD State --------------
		when ST_RWD =>

		play_stat <= REW_CODE;
		if flash_done = '1' then		-- check to see if flash has completed
			if curr_mode = '1' then		-- check current mode (play or stop)
				nxt_state <= ST_PLAY;	-- return to correct state
			else
				nxt_state <= ST_IDLE;
			end if;

		end if;
	end case;		
	end process PLAY_SM;
end behave;