parallel_port.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		parallel_port.vhd
--
-- Purpose: 	Description of interface between PC parallel port
--			and MP3 portable player.  This interface is used 
--			when the PC is downloading new MPEG songs to the 
--			MP3 portable player. 
--	
-- Created:		9-27-99 JLJ
--			Define inputs/outputs and state machine
-- Revised:		10-27-99 JLJ				
-- Revised:		11-15-99 ALS
-- **************************************************************


library ieee;
use ieee.std_logic_1164.all;

entity PARALLEL_PORT is
    port(
        
        clock		: in STD_LOGIC;
        reset		: in STD_LOGIC;
        
        -- Parallel port defined interface signals
        nStrobe		: in STD_LOGIC;			-- Active low, data is valid
        downld		: in STD_LOGIC;			-- Active high, ready to download data
        nAck		: out STD_LOGIC;			-- Active low, data rcv'd & ready for next
        dld_rdy		: out STD_LOGIC;			-- Active high, ready to begin download
        gnd_pins		: in STD_LOGIC;			-- Pins 18-25 low if parallel port connected
                
        -- MP3 portable player interface signals
        dnld_mode		: out STD_LOGIC;			-- Active high, detect download mode
        trs_rdy		: out STD_LOGIC;			-- Active high, data valid
        dnld_rdy		: in STD_LOGIC;			-- Active high, ready to transfer data
        wr_next		: in STD_LOGIC			-- Active high, ready for next transfer
                    
        );

end PARALLEL_PORT;


architecture BEHAVIOURAL of PARALLEL_PORT is

-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE 	: STD_LOGIC := '1';

-- ********************* SIGNAL DECLARATIONS ************************

-- Define states for download state machine
--type STATE is (IDLE, DOWNLOAD, DND_READY, TRS_READY, ACK, ERROR);
type STATE is (IDLE, DOWNLOAD, DND_READY, TRS_READY, ACK);
signal prs_state, nxt_state : STATE;


begin

	-- Assert transfer is ready to MP3 player only in transfer state
      trs_rdy <= '1' when (prs_state = TRS_READY) else '0';

	-- Assert nAck (data received with no errors) to PC
	nAck <= '0' when (prs_state = ACK) else '1';

	-- Identify to MP3 player when in download mode
	dnld_mode <= '0' when (prs_state = IDLE) else '1';

	-- Handshake with PC when ready for download
	dld_rdy <= '1' when (prs_state = DND_READY) else '0';


	-- ***************** Process: SEQUENTIAL ************************
	-- Purpose:  	Synchronize target state machine
	-- Components: 	none
    
    SEQUENTIAL: process(reset, clock)
    begin
        if reset = RESET_ACTIVE then	
            prs_state <= IDLE;
            
        elsif clock'event and (clock = '1') then
            prs_state <= nxt_state;
            
        end if;
    end process SEQUENTIAL;
    
    
    
    -- ******************** Process: DNLD_SM ************************
    -- Purpose: 	Target state machine to control transfer of data 
    --				in download mode between the parallel port defined
    --				interface and the designed interface for the MP3 
    --				player.  The DNLD_SM state machine manages the 
    --				handshaking needed between both components for
    --				transferring each byte of data.  
        
    DNLD_SM: process(prs_state, downld, dnld_rdy, nStrobe, wr_next, gnd_pins)
    begin
    
    	 nxt_state <= prs_state;
    	
        case prs_state is
        
        	------------------- IDLE State --------------------------
        	when IDLE =>
        		
        		-- Check if Parallel port is connected or requesting download			
        		if gnd_pins = '0' and downld = '1' then
        			nxt_state <= DOWNLOAD;		
        		end if;
        		
        	
        	------------------- DOWNLOAD State -----------------------
        	when DOWNLOAD =>
        	       		
        		-- Wait for dnld_rdy signal from MP3 player
        		if dnld_rdy = '1' then
        			nxt_state <= DND_READY;
        		end if;
        		        	
        	
        	------------------- DND_READY State ----------------------
        	when DND_READY =>
        		        		
        		-- Out of download mode, return to IDLE state        		
        		if downld = '0' then
        			nxt_state <= IDLE;      		
        		-- Wait for valid data from PC (assertion of nStrobe)			
        		elsif nStrobe = '0' then
        			nxt_state <= TRS_READY;		
        		end if;
        		
        	
        	------------------- TRS_READY State ---------------------
        	when TRS_READY =>

        		-- Wait for write and ready for next from MP3
        		
        		--elsif (wr_next = '1' and full_flash = '0') then
        		if (wr_next = '1') then

        			nxt_state <= ACK;
        			        			
        		end if;
        	
        	------------------- ACK State --------------------------
        	when ACK =>
        		
			if (nStrobe = '0') then
   		     		nxt_state <= ACK; 	
	      			
        		elsif (nStrobe = '1') then
				nxt_state <= DND_READY;

			end if;        	
        	        	
        end case;  
        
    end process DNLD_SM;
    


end BEHAVIOURAL;