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📄 cnt5.vhd

📁 MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx
💻 VHD
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-- **************************************************************
-- File:  		cnt_5.vhd
--

-- Purpose: 	Description of 5-bit address counter for the Starting 
--			Address Flash.  The address counter can be incremented
--			or decremented.  This counter holds the number of tracks
--			in the mp3 player.
--
-- Created:		11-14-99 ALS
--
-- **************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity CNT_5 is
    port(
               		
        reset		: in STD_LOGIC;				-- Sets the counter to 0	
        clock		: in STD_LOGIC;				-- Counts on rising edge of clock
        cnt_up		: in STD_LOGIC;				-- Active low, increment counter
        cnt_dn		: in STD_LOGIC;				-- Active low, decrement counter
        q_out	 	: out STD_LOGIC_VECTOR(4 downto 0)	-- 5 bit count out
                     
        );

end CNT_5;


architecture BEHAVIOURAL of CNT_5 is

-- ********************* CONSTANT DECLARATIONS ************************
constant RESET_ACTIVE : STD_LOGIC := '1';

-- ********************* SIGNAL DECLARATIONS ************************
signal q_int : UNSIGNED (4 downto 0);

begin

	-- ***************** Process: COUNTER ************************
	-- Purpose:  	Read input commands to counter.  Either increment
	--			or decrement counter if enabled.
	-- Components: 	none
    
    COUNTER: process(reset, clock)
    begin
    	
    	-- Clear counter
        if reset = RESET_ACTIVE then	
            q_int <= (others => '0');
            
        -- Load counter/increment on rising edge of clock    
        elsif clock'event and (clock = '1') then
            
  	  	-- Check if counting up or down  	
	  	if cnt_up = '1' then
			q_int <= q_int + 1;

	  	elsif cnt_dn = '1' then
			if q_int /= conv_unsigned(0,5) then
				q_int <= q_int - 1;
			end if;
	
	  	end if;
            	
                        
        end if;
        
    end process COUNTER;
    
    q_out <= STD_LOGIC_VECTOR (q_int);    
          
       
end BEHAVIOURAL;


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