power_ctrl.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		power_ctrl.vhd
--
-- Purpose: 	This file implements the Power Control Logic state
--			machine which controls the reset to the rest of the
--			circuit and turns the power off. The reset to the 
--			DS2436 Control circuit is negated first after PUP is asserted
--			so that the battery voltage can be read. The process of 
--			reading the	battery voltage takes several milli-seconds, 
--			during which the rest of the CPLD logic is held in reset. 
--			This insures that the majority of the CPLD logic is granted
--			a good, valid reset.
--
-- Created:		11/1/99	ALS
--
-- Revised:		11-14-99	ALS
-- Revised:		11-26-99	ALS
-- Revised:		2-29-00	ALS
-- **************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity power_ctrl is
  
  port(
	-- MAS3507D Interface Signals
	pup		: in		std_logic;	-- indicates that the power is above a minimum level
	wsen		: out		std_logic;	-- enables MAS3507D DC/DC convertor

	-- Main Control Logic Interface Signals
	main_rst	: out		std_logic;	-- reset for all of the other logic
	
	-- User Interface Logic Signals
	on_off	: in		std_logic;	-- indicates that the user has hit the OFF button


	-- clock	
      clock		: in		std_logic	-- 2 MHz system clock
);

end power_ctrl;

library IEEE;
use IEEE.std_logic_1164.all;

architecture behave of power_ctrl is

-- ******************** CONSTANT DECLARATIONS ***********************
-- Reset Value
constant RESET_ACTIVE	: 	std_logic := '1';

-- ********************* SIGNAL DECLARATIONS ************************

type state_type is (WAIT_PUP, WAIT_PUP_1, WAIT_PUP_2, NEGATE_RST, ASSERT_RST, PWR_OFF);

signal state, next_state : state_type;


begin


-- ************************  Power Control Logic State Machine Processes ************************
-- This process contains the combinatorial portion of the state machine
-- This state machine monitors the PUP line and the battery voltage

power_ctrl_comb: process (state, pup, on_off)
begin

	-- state machine defaults
	main_rst <= RESET_ACTIVE;
	wsen <= '1';

	-- since no reset for this circuit, set next_state to WAIT_PUP
	-- state logic will now have to set next_state to state
	next_state <= WAIT_PUP;

		case state is 
			--******************** WAIT_PUP State **************
			when WAIT_PUP =>
				-- leave this state when PUP is asserted
				if pup = '1' then
					next_state <= WAIT_PUP_1;
				end if;
				
			--******************** WAIT_PUP_1  *******************
			when WAIT_PUP_1 =>
				-- this state is simply a wait state
				-- that keeps the reset signal for the rest
				-- of the CPLD logic asserted after PUP as has
				-- asserted
				
				-- check PUP 
				if pup = '0' then
					-- PUP not stable, go back to first state
					next_state <= WAIT_PUP;
				else
					next_state <= WAIT_PUP_2;
				end if;

			--******************** WAIT_PUP_2  *******************
			when WAIT_PUP_2 =>
				-- this state is simply a wait state
				-- that keeps the reset signal for the rest
				-- of the CPLD logic asserted after PUP as has
				-- asserted
				
				-- check PUP and if user has turned player off
				if pup = '0' then
					-- PUP not stable, go back to first state
					next_state <= WAIT_PUP;
				else
					-- PUP stable for two clocks, negate reset
					next_state <= NEGATE_RST;
				end if;

			--******************** NEGATE_RST State ******************
			when NEGATE_RST =>
				
				-- negate the reset to the rest of the logic
				main_rst <= not(RESET_ACTIVE);

				-- Check PUP and if user has turned player off
				if pup = '0' or on_off = '0' then
					next_state <= ASSERT_RST;
				else
					next_state <= NEGATE_RST;
				end if;	


			--******************** ASSERT_RST State ******************
			when ASSERT_RST =>
				-- the main reset is asserted in this state
				next_state <= PWR_OFF;


			--********************* PWR_OFF ***************************
			when PWR_OFF =>
				
				-- negate the enable for the MAS3507D DC/DC convertor
				wsen <= '0';		

				-- stay in this state as power drops
				next_state <= PWR_OFF;
			
			--********************* DEFAULT **************************
			when others =>
				next_state <= WAIT_PUP;	
	
		end case;
end process;

power_ctrl_regs: process (clock)
begin
	if clock'event and clock='1' then
		state <= next_state;
	end if;
end process;

end behave;