mp3_cpld.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

			preset_lower	: inout STD_LOGIC;
			st_inc		: inout STD_LOGIC;
			st_dec		: inout STD_LOGIC;
			st_rst		: inout STD_LOGIC;
			upper_comp		: inout STD_LOGIC;
			lower_comp		: inout STD_LOGIC;

			block_tc		: in	  	STD_LOGIC;
             	SONG_ADR		: in		STD_LOGIC_VECTOR(24 downto 0);
             	TRACK			: in 		STD_LOGIC_VECTOR(4 downto 0);
             	STADR_DATA		: inout 	STD_LOGIC_VECTOR(15 downto 0);
             	SONG_END		: inout 	STD_LOGIC;
             	SONG_START		: inout 	STD_LOGIC
		);
    end component;

    
    component LCD_CONTROL
        port(
			UPD_TRACK	: in 		STD_LOGIC;
             	SONG_START	: in 		STD_LOGIC;
             	ERROR		: in 		STD_LOGIC;
             	DOWNLD	: in 		STD_LOGIC;
             	TRACK		: in 		STD_LOGIC_VECTOR(4 downto 0);
             	PLAY_STAT	: in 		STD_LOGIC_VECTOR(2 downto 0);
             	PLAY_ICON	: inout 	STD_LOGIC;
             	FWD_ICON	: inout 	STD_LOGIC;
             	RWD_ICON	: inout 	STD_LOGIC;
             	ERROR_ICON	: out 	STD_LOGIC;
             	DOWNLD_ICON	: out 	STD_LOGIC;
             	TRACK_ICON	: inout 	STD_LOGIC_VECTOR(6 downto 0);
             	CLOCK		: in 		STD_LOGIC;
             	RESET		: in 		STD_LOGIC
		);
    end component;
    
    
    component ON_OFF_LOGIC
        port(
			PWR_SWITCH	: in 		STD_LOGIC;
             	ON_OFF	: out 	STD_LOGIC;
             	CLOCK		: in 		STD_LOGIC;
             	RESET		: in 		STD_LOGIC
		);
    end component;
    

    
    component MAIN_CTRL_STATE_MACHINE
        port(
			DOWNLD_MODE	: in 		STD_LOGIC;
             	CMD		: out 	STD_LOGIC_VECTOR(1 downto 0);
             	CMD_DAT	: out 	STD_LOGIC;
             	MPEG_DONE	: in 		STD_LOGIC;
             	ERR		: in 		STD_LOGIC;
             	MAS_RST	: out 	STD_LOGIC;
             	PLAY_ST	: in 		STD_LOGIC_VECTOR(2 downto 0);
             	VOL_ADJ	: in 		STD_LOGIC;
             	MUTE_CHG	: in 		STD_LOGIC;
             	DISPLAY_ERR	: inout 	STD_LOGIC;
             	UPD_TRACK	: out 	STD_LOGIC;
             	FLASH_DONE	: in 		STD_LOGIC;
             	REW		: out 	STD_LOGIC;
             	FWD		: out 	STD_LOGIC;
             	STOP		: out 	STD_LOGIC;
             	PLAY		: inout 	STD_LOGIC;
             	WAKEUP	: out 	STD_LOGIC;
             	CLOCK		: in 		STD_LOGIC;
             	RESET		: in 		STD_LOGIC
		);
    end component;
-- 25-bit Counter
component CNT_25
	port (
		cnt_up		: in 	STD_LOGIC;					-- Active high, enable count up
      	reset			: in 	STD_LOGIC;					-- Sets the counter to 0	
      	clock			: in 	STD_LOGIC;					-- Counts on rising edge of clock
      	cnt_ld_l		: in 	STD_LOGIC;					-- Active high, load lower counter
      	cnt_ld_u		: in 	STD_LOGIC;					-- Active high, load upper counter 
      	data			: in 	STD_LOGIC_VECTOR(15 downto 0);	-- 16 bit data in        
 		preset_lower	: in 	STD_LOGIC;					-- Active high, preset lower bits
		block_tc		: inout STD_LOGIC;				-- Active high, indicates terminal count
     		q_out	 		: out STD_LOGIC_VECTOR(24 downto 0));	-- 25 bit address out
                     
end component;
   

-- 5-bit Counter
component CNT_5
	port (
		reset		: in STD_LOGIC;				 	-- Sets the counter to 0	
      	clock		: in STD_LOGIC;				 	-- Counts on rising edge of clock
      	cnt_up	: in STD_LOGIC;				 	-- Active low, increment counter
      	cnt_dn	: in STD_LOGIC;				 	-- Active low, decrement counter
      	q_out		: out STD_LOGIC_VECTOR(4 downto 0)); 	-- 4 bit count out
	
end component;


begin

    
MPEG: MPEG_CHIP_CTRL
        port map(
		     CMD 		=> CMD,
                 CMD_DAT 	=> CMD_DAT,
                 MPEG_DONE 	=> MPEG_DONE,
                 ERR 		=> ERR,
                 I2CD 		=> I2CD,
                 START 		=> START,
                 EOT 		=> EOT,
                 I2C_ERR 	=> I2C_ERR,
		     DETECT_STOP  => DETECT_STOP,
                 VOL_LVL 	=> VOL_LVL,
                 MUTE_STAT 	=> MUTE_STAT,
                 CLOCK 		=> CLOCK,
                 RESET 		=> RESET
		);
    
    I2C: I2C_MASTER
        port map(
		     SDA 	=> SDA,
                 SCL 	=> SCL,
                 I2CD 	=> I2CD,
                 START 	=> START,
                 EOT 	=> EOT,
                 I2C_ERR => I2C_ERR,
		     DETECT_STOP => DETECT_STOP,
                 CLOCK 	=> CLOCK,
                 RESET 	=> RESET
		);
    
    SOUND_CTRL: SOUND_CONTROL
        port map(
		     VOL_INC 	=> VOL_INC_BUTTON,
                 VOL_DEC 	=> VOL_DEC_BUTTON,
                 MUTE 		=> MUTE_BUTTON,
                 MPEG_DONE 	=> MPEG_DONE,
                 VOL_LVL 	=> VOL_LVL,
                 VOL_ADJ 	=> VOL_ADJ,
                 MUTE_STAT 	=> MUTE_STAT,
                 MUTE_CHG 	=> MUTE_CHG,
                 CLOCK 		=> CLOCK,
                 RESET 		=> RESET
		);
    
    PWR_CNTRL: POWER_CTRL
        port map(
		     PUP 		=> PUP,
                 WSEN	 	=> WSEN,
                 MAIN_RST 	=> RESET,
                 ON_OFF 	=> ON_OFF_SIG,
                 CLOCK 		=> CLOCK
		);
    
  
    PARLL_PORT: PARALLEL_PORT
        port map(
		     CLOCK 		=> CLOCK,
                 RESET 		=> RESET,
                 NSTROBE 	=> NSTROBE,
                 DOWNLD 	=> DOWNLD,
                 NACK 		=> NACK,
                 DLD_RDY 	=> DLD_RDY,
                 GND_PINS 	=> GND_PINS,
                 DNLD_MODE 	=> DOWNLD_MODE,
                 TRS_RDY 	=> TRS_RDY,
                 DNLD_RDY 	=> DNLD_RDY,
                 WR_NEXT 	=> WR_NEXT
		);
    
    command_sm: COMMAND_STATE_MACHINE
        port map(
		     CLOCK 		=> CLOCK,
                 RESET 		=> RESET,
                 REW 		=> REW,
                 FWD 		=> FWD,
                 STOP 		=> STOP,
                 READ_STADR 	=> READ_STADR,
                 STADR_INC 	=> STADR_INC,
                 STADR_DEC 	=> STADR_DEC,
                 CMD_SONG_END => CMD_SONG_END,
		     END_FLAG_COM	=> END_FLAG_COM,
                 TRACK 		=> TRACK,
                 ADR_LD_L 	=> ADR_LD_L,
                 ADR_LD_U 	=> ADR_LD_U,
                 FLASH_DONE 	=> FLASH_DONE
		);
    
    play_modes_comp: PLAY_MODES
        port map(
		     CLOCK 		=> CLOCK,
                 RESET 		=> RESET,
                 PLAY 		=> PLAY_BUTTON,
                 STOP 		=> STOP_BUTTON,
                 RWD 		=> REW_BUTTON,
                 FWD 		=> FWD_BUTTON,
                 FLASH_DONE 	=> FLASH_DONE,
                 PLAY_STAT 	=> PLAY_ST
		);
    
    play_logic_sm: PLAY_LOGIC_STATE_MACHINE
        port map(
		     PLAY 		=> PLAY,
                 READ 		=> READ,
                 SONG_END 	=> SONG_END,
                 EOD 		=> EOD,
                 RTR 		=> RTR,
                 PR 		=> PR,
                 CLOCK 		=> CLOCK,
                 RESET 		=> RESET
		);
    
    DOWNLOAD_INT: DNLD_INTERFACE
        port map(
		     CLOCK 		=> CLOCK,
                 RESET 		=> RESET,
                 DNLD_MODE 	=> DOWNLD_MODE,
                 TRS_RDY 	=> TRS_RDY,
                 SONG_ST 	=> SONG_ST,
                 DNLD_RDY 	=> DNLD_RDY,
                 WR_NEXT 	=> WR_NEXT,
		     LAST_BYTE	=> LAST_BYTE,
		     FLASH_CMD	=> FLASH_CMD,
                 END_WRITE_ERS => END_WRITE_ERS,
			DNLD_CNT_RST => DNLD_CNT_RST
		);
    
    flash_cntrl: FLASH_CNTR
        port map(
		     CLOCK 		=> CLOCK,
                 RESET 		=> RESET,
                 DOWNLD_MODE 	=> DOWNLD_MODE,
		     FLASH_CMD	=> FLASH_CMD,
                 END_WRITE_ERS => END_WRITE_ERS,
                 DATA 		=> PARALLEL_PORT_DATA,
                 FLASH_DATA 	=> SONG_DATA,
		     LAST_BYTE	=> LAST_BYTE,
                 PLAY 		=> PLAY,
                 WAKEUP 	=> WAKEUP,
                 READ 		=> READ,
                 READ_STADR 	=> READ_STADR,
                 REW 		=> REW,
                 FWD 		=> FWD,
                 STOP 		=> STOP,
                 SONG_EN 	=> SONG_EN,
                 SONG_OUT 	=> SONG_OUT,
                 SONG_WR 	=> SONG_WR,
                 SONG_STS 	=> SONG_STS,
                 RP_N 		=> RP_N,
                 STADR_EN 	=> STADR_EN,
                 STADR_out 	=> STADR_out,
                 STADR_WR 	=> STADR_WR,
                 STADR_STS 	=> STADR_STS,
                 STADR_INC 	=> STADR_INC,
                 STADR_DEC 	=> STADR_DEC,
		     DNLD_CNT_RST	=> DNLD_CNT_RST,
                 CMD_SONG_END => CMD_SONG_END,
		     END_FLAG_COM	=> END_FLAG_COM,
			-- Test Outputs
			adr_up		=> adr_up,
			preset_lower	=> preset_lower,
			st_inc		=> st_inc,
			st_dec		=> st_dec,
			st_rst		=> st_rst,
			upper_comp		=> upper_comp,
			lower_comp		=> lower_comp,
			--ucomp			=> ucomp,
			--lcomp			=> lcomp,
			block_tc		=> block_tc,

                 SONG_ADR 	=> SONG_ADR,
                 TRACK 		=> TRACK,
                 STADR_DATA 	=> START_ADDRESS,
                 SONG_END 	=> SONG_END,
                 SONG_START 	=> SONG_START
		);
    
    lcd_cntrl: LCD_CONTROL
        port map(
		     UPD_TRACK 	=> UPD_TRACK,
                 SONG_START 	=> SONG_START,
                 ERROR 		=> DISPLAY_ERR,
                 DOWNLD 	=> DOWNLD_MODE,
                 TRACK 		=> TRACK,
                 PLAY_STAT 	=> PLAY_ST,
                 PLAY_ICON 	=> PLAY_ICON,
                 FWD_ICON 	=> FWD_ICON,
                 RWD_ICON 	=> RWD_ICON,
                 ERROR_ICON 	=> ERROR_ICON,
                 DOWNLD_ICON 	=> DOWNLD_ICON,
                 TRACK_ICON 	=> TRACK_ICON,
                 CLOCK 		=> CLOCK,
                 RESET 		=> RESET
		);
    
    ON_OFF_COMP: ON_OFF_LOGIC
        port map(
		     PWR_SWITCH 	=> ON_OFF_BUTTON,
                 ON_OFF 	=> ON_OFF_SIG,
                 CLOCK 		=> CLOCK,
                 RESET 		=> RESET
		);
    
    MAIN_CONTROL_SM: MAIN_CTRL_STATE_MACHINE
        port map(
		     DOWNLD_MODE 	=> DOWNLD_MODE,
                 CMD 		=> CMD,
                 CMD_DAT 	=> CMD_DAT,
                 MPEG_DONE 	=> MPEG_DONE,
                 ERR 		=> ERR,
                 MAS_RST 	=> MAS_RST,
                 PLAY_ST 	=> PLAY_ST,
                 VOL_ADJ 	=> VOL_ADJ,
                 MUTE_CHG 	=> MUTE_CHG,
                 DISPLAY_ERR 	=> DISPLAY_ERR,
                 UPD_TRACK 	=> UPD_TRACK,
                 FLASH_DONE 	=> FLASH_DONE,
                 REW 		=> REW,
                 FWD		=> FWD,
                 STOP 		=> STOP,
                 PLAY 		=> PLAY,
                 WAKEUP 	=> WAKEUP,
                 CLOCK 		=> CLOCK,
                 RESET 		=> RESET
	);
	-- Song Address Counter
	SONG_CNT : CNT_25
		port map (
			cnt_up		=> adr_up,
      		reset			=> st_rst,
      		clock			=> clock,
      		cnt_ld_l		=> adr_ld_l,
      		cnt_ld_u		=> adr_ld_u,
      		data			=> start_address,
			preset_lower 	=> preset_lower,
			block_tc		=> block_tc,
      		q_out	 		=> SONG_ADR	
			);        

	-- Starting Address Couner
	STADR_CNT : CNT_5
		port map (
      		reset		=> st_rst,
      		clock		=> clock,
      		cnt_up	=> st_inc,
      		cnt_dn	=> st_dec,
      		q_out		=> TRACK 
			);
  
end archMP3_CPLD;