📄 mp3_cpld.vhd
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-- **************************************************************
-- File: mp3_cpld.vhd
--
-- Purpose: This file implements all of the CoolRunner CPLD functions
-- for the MP3 portable player. This is the top-level design
-- which connects all of the VHDL components using structural VHDL.
--
-- This file was orignally generated using WorkView Office. A schematic
-- was created and the structural VHDL was exported. The file was then
-- formatted and comments added.
--
-- Created: 11/10/99 ALS
--
-- Revised: 11/15/99 ALS
-- Revised: 11/16/99 ALS
-- Revised: 11/17/99 ALS
-- Revised: 11/24/99 ALS
-- Revised: 11/26/99 ALS
-- Revised: 11/26/99 ALS
-- Revised: 11/28/99 ALS
-- Revised: 12/2/99 ALS
-- Revised: 12/6/99 ALS
-- Revised: 02/22/00 ALS
-- Revised: 02/23/00 ALS
-- Revised: 02/29/00 ALS
-- ************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MP3_CPLD is
port(
-- Starting Address Flash Interface Signals
START_ADDRESS : inout std_logic_vector(15 downto 0); -- data
TRACK : inout std_logic_vector(4 downto 0); -- address
STADR_STS : in std_logic; -- ready/Busy flag
STADR_EN : out std_logic; -- chip enable
STADR_WR : out std_logic; -- write enable
STADR_OUT : out std_logic; -- output enable
-- Reset signal for both flash modules (active low)
RP_N : out std_logic;
-- Song Flash Interface Signals
SONG_DATA : inout std_logic_vector(7 downto 0); -- data
SONG_ADR : inout std_logic_vector(24 downto 0); -- address
SONG_STS : in std_logic; -- ready/busy flag
SONG_EN : out std_logic; -- chip enable
SONG_WR : out std_logic; -- write enable
SONG_OUT : out std_logic; -- output enable
-- Parallel Port Interface Signals
PARALLEL_PORT_DATA : in std_logic_vector(7 downto 0); -- data
LAST_BYTE : in std_logic; -- indicates data byte is the last byte of
-- MP3 data
DLD_RDY : out std_logic; -- CPLD is ready for download
SONG_ST : in std_logic; -- data is the start of a new song
NACK : out std_logic; -- acknowledge - indicates that CPLD has received the data
GND_PINS : in std_logic; -- signals set to GND that indicate the portable player
-- is connected to the PC parallel port
DOWNLD : in std_logic; -- PC is ready to begin download operation
NSTROBE : in std_logic; -- indicates that the data on the bus is valid
-- User Interface Signals
MUTE_BUTTON : in std_logic; -- mute button
ON_OFF_BUTTON : in std_logic; -- on/off button
VOL_DEC_BUTTON : in std_logic; -- volume decrement button
VOL_INC_BUTTON : in std_logic; -- volume increment button
PLAY_BUTTON : in std_logic; -- play button
REW_BUTTON : in std_logic; -- rewind button
FWD_BUTTON : in std_logic; -- fast forward button
STOP_BUTTON : in std_logic; -- stop button
-- LCD Display Signals
TRACK_ICON : inout std_logic_vector(6 downto 0); -- signals to drive the track 7-segment display
FWD_ICON : inout std_logic; -- signal to drive fwd icon
RWD_ICON : inout std_logic; -- signal to drive rew icon
ERROR_ICON : out std_logic; -- signal to drive error icon
DOWNLD_ICON : out std_logic; -- signal to drive downld icon
PLAY_ICON : inout std_logic; -- signal to drive play icon
-- MAS3507D Interface Signals
MAS_RST : out std_logic; -- active low reset
WSEN : inout std_logic; -- active high enable
PUP : in std_logic; -- power supply is above minimum level
EOD : in std_logic; -- PIO-DMA end of data signal
PR : out std_logic; -- indicates sending of data
RTR : in std_logic; -- active low signal indicating data has been received
-- DAC3550A Interface Signals
SCL : inout std_logic; -- I2C clock
SDA : inout std_logic; -- I2C data
-- System Clock
CLOCK : in std_logic
);
end MP3_CPLD;
architecture archMP3_CPLD of MP3_CPLD is
-- ********************* SIGNAL DECLARATIONS ************************
-- I2C Signals
signal CMD : std_logic_vector(1 downto 0);
signal I2CD : std_logic_vector(7 downto 0);
signal CMD_DAT : std_logic;
signal START : std_logic;
signal EOT : std_logic;
signal ERR : std_logic;
signal DETECT_STOP : std_logic;
-- User Interface Signals
signal VOL_LVL : std_logic_vector(5 downto 0);
signal PLAY_ST : std_logic_vector(2 downto 0);
signal ON_OFF_SIG : std_logic;
signal MUTE_CHG : std_logic;
signal MUTE_STAT : std_logic;
signal VOL_ADJ : std_logic;
signal DISPLAY_ERR : std_logic;
signal UPD_TRACK : std_logic;
-- Power Management Signals
signal RESET : std_logic;
-- Parallel Port/Download Signals
signal DNLD_RDY : std_logic;
signal TRS_RDY : std_logic;
signal WR_NEXT : std_logic;
-- Flash Control Signals
signal SONG_END : std_logic;
signal CMD_SONG_END : std_logic;
signal SONG_START : std_logic;
signal ADR_LD_U : std_logic;
signal ADR_LD_L : std_logic;
signal STADR_DEC : std_logic;
signal STADR_INC : std_logic;
signal READ : std_logic;
signal READ_STADR : std_logic;
signal END_FLAG_COM : std_logic;
signal FLASH_CMD : std_logic_vector(2 downto 0);
signal END_WRITE_ERS: std_logic;
signal WAKEUP : std_logic;
signal block_tc : std_logic;
signal adr_up : STD_LOGIC;
signal preset_lower : STD_LOGIC;
signal st_inc : STD_LOGIC;
signal st_dec : STD_LOGIC;
signal st_rst : STD_LOGIC;
signal dnld_cnt_rst : STD_LOGIC;
-- Debug/test signals that were I/O
signal upper_comp : std_logic;
signal lower_comp : std_logic;
signal i2c_err : std_logic;
signal play : std_logic;
signal stop : std_logic;
signal fwd : std_logic;
signal rew : std_logic;
signal FLASH_DONE : std_logic;
signal MPEG_DONE : std_logic;
signal DOWNLD_MODE : std_logic;
-- ********************* COMPONENT DECLARATIONS ************************
component MPEG_CHIP_CTRL
port(
CMD : in STD_LOGIC_VECTOR(1 downto 0);
CMD_DAT : in STD_LOGIC;
MPEG_DONE : out STD_LOGIC;
ERR : out STD_LOGIC;
I2CD : inout STD_LOGIC_VECTOR(7 downto 0);
START : out STD_LOGIC;
EOT : in STD_LOGIC;
I2C_ERR : in STD_LOGIC;
DETECT_STOP : in STD_LOGIC;
VOL_LVL : in STD_LOGIC_VECTOR(5 downto 0);
MUTE_STAT : in STD_LOGIC;
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component I2C_MASTER
port(
SDA : inout STD_LOGIC;
SCL : inout STD_LOGIC;
I2CD : in STD_LOGIC_VECTOR(7 downto 0);
START : in STD_LOGIC;
EOT : out STD_LOGIC;
I2C_ERR : out STD_LOGIC;
DETECT_STOP : inout STD_LOGIC;
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component SOUND_CONTROL
port(
VOL_INC : in STD_LOGIC;
VOL_DEC : in STD_LOGIC;
MUTE : in STD_LOGIC;
MPEG_DONE : in STD_LOGIC;
VOL_LVL : inout STD_LOGIC_VECTOR(5 downto 0);
VOL_ADJ : out STD_LOGIC;
MUTE_STAT : inout STD_LOGIC;
MUTE_CHG : inout STD_LOGIC;
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component POWER_CTRL
port(
PUP : in STD_LOGIC;
WSEN : out STD_LOGIC;
MAIN_RST : out STD_LOGIC;
ON_OFF : in STD_LOGIC;
CLOCK : in STD_LOGIC
);
end component;
component PARALLEL_PORT
port(
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
NSTROBE : in STD_LOGIC;
DOWNLD : in STD_LOGIC;
NACK : out STD_LOGIC;
DLD_RDY : out STD_LOGIC;
GND_PINS : in STD_LOGIC;
DNLD_MODE : out STD_LOGIC;
TRS_RDY : out STD_LOGIC;
DNLD_RDY : in STD_LOGIC;
WR_NEXT : in STD_LOGIC
);
end component;
component COMMAND_STATE_MACHINE
port(
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
REW : in STD_LOGIC;
FWD : in STD_LOGIC;
STOP : in STD_LOGIC;
READ_STADR : out STD_LOGIC;
STADR_INC : out STD_LOGIC;
STADR_DEC : out STD_LOGIC;
CMD_SONG_END : out STD_LOGIC;
END_FLAG_COM : in STD_LOGIC;
TRACK : in STD_LOGIC_VECTOR(4 downto 0);
ADR_LD_L : out STD_LOGIC;
ADR_LD_U : out STD_LOGIC;
FLASH_DONE : out STD_LOGIC
);
end component;
component PLAY_MODES
port(
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
PLAY : in STD_LOGIC;
STOP : in STD_LOGIC;
RWD : in STD_LOGIC;
FWD : in STD_LOGIC;
FLASH_DONE : in STD_LOGIC;
PLAY_STAT : out STD_LOGIC_VECTOR(2 downto 0)
);
end component;
component PLAY_LOGIC_STATE_MACHINE
port(
PLAY : in STD_LOGIC;
READ : out STD_LOGIC;
SONG_END: in STD_LOGIC;
EOD : in STD_LOGIC;
RTR : in STD_LOGIC;
PR : out STD_LOGIC;
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component DNLD_INTERFACE
port(
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
DNLD_MODE : in STD_LOGIC;
TRS_RDY : in STD_LOGIC;
SONG_ST : in STD_LOGIC;
DNLD_RDY : out STD_LOGIC;
WR_NEXT : out STD_LOGIC;
LAST_BYTE : in STD_LOGIC;
FLASH_CMD : out STD_LOGIC_VECTOR(2 downto 0);
END_WRITE_ERS: in STD_LOGIC;
DNLD_CNT_RST : out STD_LOGIC
);
end component;
component FLASH_CNTR
port(
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
DOWNLD_MODE : in STD_LOGIC;
FLASH_CMD : in STD_LOGIC_VECTOR(2 downto 0);
END_WRITE_ERS: out STD_LOGIC;
DATA : in STD_LOGIC_VECTOR(7 downto 0);
FLASH_DATA : out STD_LOGIC_VECTOR(7 downto 0);
LAST_BYTE : in STD_LOGIC;
PLAY : in STD_LOGIC;
WAKEUP : in STD_LOGIC;
READ : in STD_LOGIC;
READ_STADR : in STD_LOGIC;
REW : in STD_LOGIC;
FWD : in STD_LOGIC;
STOP : in STD_LOGIC;
SONG_EN : out STD_LOGIC;
SONG_OUT : out STD_LOGIC;
SONG_WR : out STD_LOGIC;
SONG_STS : in STD_LOGIC;
RP_N : out STD_LOGIC;
STADR_EN : out STD_LOGIC;
STADR_OUT : out STD_LOGIC;
STADR_WR : out STD_LOGIC;
STADR_STS : in STD_LOGIC;
STADR_INC : in STD_LOGIC;
STADR_DEC : in STD_LOGIC;
DNLD_CNT_RST : in STD_LOGIC;
CMD_SONG_END: in STD_LOGIC;
END_FLAG_COM: inout STD_LOGIC;
-- Test Outputs
adr_up : inout STD_LOGIC;
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