upcnt4.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		upcnt4.vhd
--
-- Purpose: 	4-bit up counter to count I2C serial data bits
--	
-- Created:		10/13/99 JLJ
--
-- Revised:		11-14-99 ALS
-- **************************************************************



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


entity upcnt4 is
	port(
	      
	     data         : in STD_LOGIC_VECTOR (3 downto 0);    -- Serial data in
	     cnt_en       : in STD_LOGIC;                        -- Count enable
	     load         : in STD_LOGIC;                        -- Load line enable
 	     reset          : in STD_LOGIC;                        -- Active low clear
	     clock          : in STD_LOGIC;                        -- Clock
	     qout         : out STD_LOGIC_VECTOR (3 downto 0)
		
	     );
		
end upcnt4;



architecture DEFINITION of upcnt4 is

-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE : std_logic := '1';

-- ******************** SIGNAL DECLARATIONS ***********************
signal q_int : UNSIGNED (3 downto 0);

begin

-- ******************** Count Process ***********************

count_proc: process(clock, reset)
     begin
          
          -- Clear output register
          if (reset = RESET_ACTIVE) then
	       q_int <= (others => '0');
	       
	  -- On rising edge of clock count
	  elsif (clock'event) and clock = '1' then

	       -- Load in start value
	       if (load = '1') then
		    q_int <= UNSIGNED(data);
	       -- If count enable is high
	       elsif cnt_en = '1' then
		    q_int <= q_int + 1;
	       end if;
	  end if;

     end process;

     qout <= STD_LOGIC_VECTOR(q_int);

end DEFINITION;