sound_control.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		sound_control.vhd
--
-- Purpose: 	This file implements the Sound Control section of the
--			user interface.  This module input and outputs are 
--			described below. All inputs are processed on the rising
--			edge of the specific input signal.
--
--			Inputs:
--			- vol_inc: signal from user interface that volume is
--			  being adjusted up by one unit. 
--			- vol_dec: signal from user interface that volume is
--			  being adjusted down by one unit. 
--			- mute: signal from user interface that mute is turned 
--			  on/off.
--			- mpeg_done - signal from main logic signifying that
--			  volume adjustment has completed
--		
--			Outputs:
--			- vol_lvl[5:0]: vector specifying the adjusted volume level
--			- vol_adj: rising edge signal that volume has changed
--			- mute_stat: signal specifying whether mute is on/off
--			- mute_change: rising edge signal that mute has changed
--
-- Created:		10/21/99	CLH 
-- Revised:		10/27/99	ALS
-- Revised:		11/28/99	ALS
-- Revised:		02/23/00	ALS
-- **************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity sound_control is
  
  port(
	-- *********** input signals ***********************************
	vol_inc	: in STD_LOGIC;
	vol_dec	: in STD_LOGIC;
	mute 		: in STD_LOGIC;
	mpeg_done	: in STD_LOGIC;

	-- *********** output signals **********************************
	vol_lvl	: inout STD_LOGIC_VECTOR(5 downto 0);
	vol_adj	: out STD_LOGIC;
	mute_stat	: inout STD_LOGIC;
	mute_chg	: inout STD_LOGIC;

	-- *********** standard input signals **************************
	clock 	: in STD_LOGIC;
	reset		: in STD_LOGIC
	);
end sound_control;

architecture behave of sound_control is

	-- ************************* CONSTANT DECLARATIONS *****************
	--  standard signals 
	constant RESET_ACTIVE	: STD_LOGIC := '1';
	constant REG_DELAY	: time := 3 ns;

	--  volume setting constants 
	constant MAX_VOL	: std_logic_vector (5 downto 0) := "111000";
	constant MIN_VOL	: std_logic_vector (5 downto 0) := "001100";
	constant LOW_VOL_BITS	: std_logic_vector(1 downto 0) := "00"; -- lower bits of volume
											     -- level stay at default

	-- ************************ COMPONENT DECLARATIONS *****************
	-- Up/Down 4 bit counter 
	--	This counter will load in the default value "101" at reset
	component UPDWNCNT4
		port(
	     		up		 : in std_logic;
			down		 : in std_logic;
	     		qout         : out std_logic_vector (3 downto 0);
 	     		reset        : in std_logic;                       -- Active high reset
	     		clock        : in std_logic                        -- Clock
	     	);
		
	end component;


	-- ******************** SIGNAL DECLARATIONS ***********************

	--  Define states for volume control 
	type STATE_TYPE is (ST_IDLE, ST_MAX_CHK, ST_MIN_CHK, ST_ADJ);	
	signal state, next_state : STATE_TYPE;

	--  define combinatorial signals for process 
	signal vol_adj_com 	: STD_LOGIC;	-- variable for combinatorial mute status
	
	--  These signals are used to detect a rising edge of the specified signal. 
	signal vol_inc_reg	: STD_LOGIC;
	signal vol_dec_reg	: STD_LOGIC;
	signal mute_reg		: STD_LOGIC;
	signal vol_inc_re		: STD_LOGIC;
	signal vol_dec_re		: STD_LOGIC;
	

	-- Counter interface signals
	signal up, down		: std_logic;	-- up, down counter controls	
	signal vol_cnt		: std_logic_vector(3 downto 0); -- counter output	

begin

-- only use a 4-bit counter for the volume, vol_lvl is this value with "00" appended
vol_lvl <= vol_cnt & LOW_VOL_BITS;

-- ************* Process: INPUT_REG **************
-- Purpose: provide registered value that will be
-- used in the PLAY_SM process to determine if input
-- signal is a rising edge


	INPUT_REG: process(reset, clock)
	begin
		if reset =  RESET_ACTIVE then	
			vol_inc_reg <= '0' ;
			vol_dec_reg <= '0' ;
			mute_reg <= '0' ;

		elsif clock'event and (clock = '1') then
			vol_inc_reg <= vol_inc ;
			vol_dec_reg <= vol_dec ;
			mute_reg <= mute ;

		end if;		

	end process INPUT_REG;

-- set rising edge signals
vol_inc_re <= '1' when vol_inc = '1' and vol_inc_reg = '0'
			else '0';
vol_dec_re <= '1' when vol_dec = '1' and vol_dec_reg = '0'
			else '0';

	-- ************* Process: SEQUENTIAL **************
	-- Purpose: Synchronize target state machine
	-- Components: None

	SEQUENTIAL: process(reset, clock)
	begin
		if reset =  RESET_ACTIVE then
			state <= ST_IDLE ;
			vol_adj <= '0' ;

		elsif clock'event and (clock = '1') then
			state <= next_state ;
			vol_adj <= vol_adj_com ;

		end if;
	end process SEQUENTIAL;

	
	-- ************* Process: MUTE_CHG **************
	-- Purpose: Keep track of mute status. Mute toggles on/off 
	--          when mute is asserted
	-- Components: None
	MUTE_STATES: process(reset, clock)
	begin
	if reset = RESET_ACTIVE then
		mute_stat <= '0' ;
		mute_chg <= '0' ;
	elsif clock'event and clock = '1' then
		if(mute_reg = '0' and mute = '1') then  -- detect rising edge of mute signal
			-- toggle status of mute
			mute_stat <= not(mute_stat) ;	
			mute_chg <= '1' ;

		else
			mute_stat <= mute_stat ;
			mute_chg <= '0' ;

		end if;
	end if;

	end process MUTE_STATES;


	-- ************* Process: VOL_SM **************
	-- Purpose: Target state machine to define volume levels
	-- Components: None
	VOL_SM: process(state, vol_inc_re, vol_dec_re, mpeg_done, vol_lvl)
	begin

	next_state <= state;	-- reset state variable
	up <= '0';			-- hold counter constant
	down <= '0';		-- hold counter constant
	vol_adj_com <= '0';


	case state is

		------------- ST_IDLE State --------------
		when ST_IDLE =>
			if vol_inc_re = '1' then
				next_state <= ST_MAX_CHK;
				vol_adj_com <= '1';

			elsif vol_dec_re = '1' then
				next_state <= ST_MIN_CHK;
				vol_adj_com <= '1';

			end if;


		------------- ST_MAX_CHK State --------------
		when ST_MAX_CHK =>
			if vol_lvl = MAX_VOL then
				-- volume is at max, no need to increment
				-- return to IDLE state
				next_state <= ST_IDLE;
		
			else
				-- increment the volume and go to the state 
				-- that waits for mpeg_done
				up <= '1';
				next_state <= ST_ADJ;
			end if;

		------------- ST_MIN_CHK State --------------
		when ST_MIN_CHK =>
			if vol_lvl = MIN_VOL then
				-- volume level is at minimum, no need to decrement
			next_state <= ST_IDLE;
		
		else
			-- decrement the volume and go to the state that waits
			-- for MPEG_DONE
			down <= '1';
			next_state <= ST_ADJ;
		end if;

		------------- ST_ADJ State ------------------
		when ST_ADJ	=>
			if mpeg_done = '1' then	
				next_state <= ST_IDLE;
			end if;

	end case;		
	end process VOL_SM;

-- *************************** Volume Counter Instantiation *******************
	VOLUME_COUNTER : UPDWNCNT4
	  port map(  up		=> up,
			down		=> down,
			qout		=> vol_cnt,
			reset		=> reset,
			clock		=> clock
			);


end behave;