play_logic_state_machine.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		play_logic_state_machine.vhd
--
-- Purpose: 	This file implements the Play Logic state machine
--			which performs the necessary handshaking to perform
--			the parallel data transfer of MP3 data to the MAS3507D.
--
--			When the MAS3507D is ready and negates end-of-data (EOD),
--			this state machine gets data from the flash and asserts PR.
--			It then waits for RTR to assert and then negate. PR is then
--			negated. When PR is negated, the READ signal to the flash is negated
--			and the Flash Read State Machine increments the flash address and 
--			gets the next data word. 
--
--			When SONG_END asserts indicating the end of MP3 data in the song flash,
--			this state machine resets the MAS3507D and returns to the IDLE state.
--
-- Created:		10/20/99	ALS
--
-- Revised:		11/5/99 	ALS
-- Revised:		01/13/00 	ALS
-- Revised:		01/17/00	ALS
-- Revised:		01/19/00	ALS 
-- Revised:		01/20/00 	ALS
-- Revised:		02/03/00	ALS
-- **************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity play_logic_state_machine is
  
  port(
	-- Main Control Logic State Machine Interface Signals
	play		: in		std_logic;	-- indicates a play operation is enabled

	-- Flash Control Logic Interface Signals
	read 		: out 	std_logic;	-- read data from flash
	song_end	: in		std_logic;  -- indicates end of song data in song flash

	-- MAS3507D Interface Signals
	--wrdy		: in		std_logic;	-- indicates that MAS3507D is ready
	eod		: in		std_logic;	-- active low signal indicating end of data from MAS3507D
	rtr		: in		std_logic;	-- active low signal indicating MAS3507D obtained data
	pr		: out		std_logic;	-- active high signal indicating new data is available

	-- clock and reset	
      clock		: in		std_logic;	-- 2 MHz system clock
	reset 	: in 		std_logic	-- system reset
);

end play_logic_state_machine;

library IEEE;
use IEEE.std_logic_1164.all;

architecture behave of play_logic_state_machine is

-- ******************** CONSTANT DECLARATIONS ***********************
-- Reset Value
constant RESET_ACTIVE	: 	std_logic := '1';

-- ********************* SIGNAL DECLARATIONS ************************

--type state_type is (IDLE, FLASH_DATA, ASSERT_PR, WAIT_RTR, NEGATE_PR);
type state_type is (IDLE, FLASH_DATA, ASSERT_PR, NEGATE_PR);

signal state, next_state : state_type;

signal pr_com		: std_logic;	-- combinatorial pr from state machine
signal rtr_low		: std_logic;	-- =1 when falling edge of RTR occurs
signal rtr_reg_reset	: std_logic;	-- resets the register that captures RTR falling edge


begin

-- ************************  RTR Low Processes ************************
-- This process contains a register clocked by the falling edge of RTR to
-- indicate that RTR is low
rtr_low_proc: process(rtr, rtr_reg_reset)
begin
	if rtr_reg_reset = RESET_ACTIVE then
		rtr_low <= '0';
	elsif rtr'event and rtr = '0' then
		rtr_low <= '1';
	end if;
end process;

-- ************************  Play Logic State Machine Processes ************************
-- This process contains the combinatorial portion of the state machine
-- This state machine performs the handshaking for the parallel DMA data transfer to the
-- MAS3507D

play_logic_comb: process (state, eod, song_end, rtr, rtr_low, play)
begin

-- state machine defaults
	read <= '0';
	pr_com <= '0';
	next_state <= state;
	rtr_reg_reset <= not(RESET_ACTIVE);

		case state is 
			--******************** IDLE State **************
			when IDLE =>

				-- reset the RTR falling edge register
				rtr_reg_reset <= RESET_ACTIVE;

				-- leave this state when MAS3507D is ready, EOD is	
				-- negated, and play is asserted and song_end is negated
				if eod = '1'  and play = '1'  and song_end = '0' then
					next_state <= FLASH_DATA;
				end if;
			
			--******************** FLASH_DATA State ***************
			when FLASH_DATA =>
				-- this state asserts the READ signal to the Flash
				-- Control Logic state machine
				if song_end = '0' and play = '1' then
					read <= '1';
				end if;
				
				if play = '0' then 
					next_state <= IDLE;
				elsif eod = '1' then 
					next_state <= ASSERT_PR;
				end if;


			--******************** ASSERT_PR State ******************
			when ASSERT_PR =>
				-- this state aserts the PR signal and waits for RTR to assert
				pr_com <= '1';
				-- keep read asserted so that flash data does not change
				read <= '1';

				-- If eod asserts, return to FLASH_DATA state
				-- else if rtr has gone low and is now high, negate PR
				-- RTR_LOW indicates that a RTR falling edge has occurred
				if eod = '0' then
					next_state <= FLASH_DATA;
				elsif rtr_low = '1' and rtr = '1' then
					next_state <= NEGATE_PR;
				end if;			
		
			--******************** WAIT_RTR State ******************
			--when WAIT_RTR =>
				-- wait in this state for RTR to negate indicating that
				-- the MAS3507D has received the data
				-- keep pr and read asserted
			--	pr_com <= '1';
			--	read <= '1';

			--	if rtr = '1' then
					-- rtr negated, go to negate_pr state
			--		next_state <= NEGATE_PR;
			--	end if;


			--******************** NEGATE_PR State ******************
			when NEGATE_PR =>
				-- negate PR and READ signal
				-- negation of the READ signal transitions the READ flash
				-- state machine to the INC_ADDR state and gets new data ready
				--pr_com <= '0';
				--read <= '0';
				next_state <= IDLE; 

			
			--********************* DEFAULT **************************
			when others =>
				next_state <= IDLE;	
	
		end case;
end process;

play_logic_state_machine_regs: process (clock, reset)
begin
	if reset = RESET_ACTIVE then
		state <= IDLE;
	elsif clock'event and clock='1' then
		state <= next_state;
	end if;
end process;

pr_fallingedge_regs: process (clock, reset)
begin
	if reset = RESET_ACTIVE then
		pr <= '0';
	elsif clock'event and clock='0' then
		pr <= pr_com;
	end if;
end process;

end behave;