cnt25.vhd

MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx

-- **************************************************************
-- File:  		cnt_25.vhd
--

-- Purpose: 	Description of 25-bit address counter for the Song 
--			Address Flash.  32MBytes of address space are byte wide
--			with 2^25 address locations.  The address counter 
--			can be either incremented or loaded with a 25-bit address.
--			The counter must be enabled to be active.
--	
-- Created:		10-10-99 JLJ
-- Revised:		10-21-99 JLJ
-- Revised:		11-7-99 ALS
-- Revised:		11-9-99 JLJ
-- Revised:		11-14-99 ALS
-- **************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity CNT_25 is
    port(
               		
        cnt_up		: in STD_LOGIC;			-- Active high, count up
        reset		: in STD_LOGIC;			-- Sets the counter to 0	
        clock		: in STD_LOGIC;			-- Counts on rising edge of clock
        cnt_ld_l		: in STD_LOGIC;			-- Active high, load lower counter
	  cnt_ld_u		: in STD_LOGIC;			-- Active high, load upper counter
        data		: in STD_LOGIC_VECTOR(15 downto 0);	-- 16 bit data in  
	  preset_lower	: in STD_LOGIC;				-- preset lower bits
	  block_tc		: inout STD_LOGIC;			-- terminal count      
        q_out	 	: out STD_LOGIC_VECTOR(24 downto 0)	-- 24 bit address out
                     
        );

end CNT_25;


architecture BEHAVIOURAL of CNT_25 is

-- ********************* CONSTANT DECLARATIONS ************************
constant RESET_ACTIVE 	: std_logic := '1';
constant PRESET_ACTIVE 	: std_logic := '1';
constant ALL_ONES		: UNSIGNED(6 downto 0) := (others => '1');

-- ********************* SIGNAL DECLARATIONS ************************
signal q_int : UNSIGNED (24 downto 0);

begin



	-- ***************** Process: COUNTER ************************
	-- Purpose:  	Read input commands to counter.  Either load
	--				counter or increment present value.
    
    COUNTER: process(reset, clock)
    begin
    	
    	-- Clear counter
        if (reset = RESET_ACTIVE) then	
            q_int <= (others => '0');  
            
        -- Load counter/increment on rising edge of clock    
        elsif clock'event and (clock = '1') then
            if (preset_lower = PRESET_ACTIVE) then
			-- preset lower 18 bits so that counter will index
			-- into memory blocks
			q_int(17 downto 0) <= (others => '1');
		
		-- Load upper and lower portions of 25-bit counter
            elsif cnt_ld_l = '1' then
            	q_int(15 downto 0) <= UNSIGNED (data);
		
            elsif cnt_ld_u = '1' then
			q_int(24 downto 16) <= UNSIGNED (data(8 downto 0));

            elsif cnt_up = '1' then
            	q_int <= q_int + 1;
		end if;
            	
        end if;
        
    end process COUNTER;
  
	-- ***************** Process: Terminal Count ************************
	-- Purpose:  Determine when upper 7 bits of counter are all 1

tc_proc: process (reset, clock)

begin
	if reset = RESET_ACTIVE then
		block_tc <= '0';
	elsif clock'event and clock = '1' then
		-- Check for terminal count
		if q_int(24 downto 18) = ALL_ONES then
			block_tc <= '1';
		end if;
	end if;
end process;
  
    q_out <= STD_LOGIC_VECTOR (q_int);    
          
       
end BEHAVIOURAL;