crc32_d32_tb.v

能算出CRC32 Data width 32 bit 的HDL

module crc_tb(); 

reg [31:0] DATA_IN; 
reg CLK; 
reg RESET; 
reg init; 
reg START; 
wire [31:0] CRC_OUT; 
wire [31:0] neg_crc; 
wire [31:0] crc; 

CRC32_D32 u1(DATA_IN, CLK, RESET, START, init, CRC_OUT,neg_crc,crc); 

initial 
CLK <= 1'b1; 
always 
#5 CLK <= ~ CLK; 

initial 
begin 
RESET <= 1'b0; 
#10 RESET <= 1'b1; 
end 


initial 
begin 
init <= 1'b0; 
#10 init <= 1'b1; 
#10 init <= 1'b0; 
end 

initial 
begin 
START <= 1'b0; 
#30 START <= 1'b1; 
//#150 START <= 1'b0; 
#30 START <= 1'b0; 
end 

initial 
begin 
//8040C020A0604040C020A060007455AAAA55AA5555AA55AAAA55AA5555AA55AAAA55AA5555AA55AAAA55AA5555AA55AAAA55AA5555AA55AAAA55AA55 
DATA_IN <= 32'h0; 
#30 DATA_IN <= 32'h8040C020; 
#10 DATA_IN <= 32'hA0604040; 
#10 DATA_IN <= 32'hC020A060; 
#10 DATA_IN <= 32'h007455AA; 
#10 DATA_IN <= 32'hAA55AA55; 
#10 DATA_IN <= 32'h55AA55AA; 
#10 DATA_IN <= 32'hAA55AA55;
 
#10 DATA_IN <= 32'h55AA55AA; 
#10 DATA_IN <= 32'hAA55AA55; 
#10 DATA_IN <= 32'h55AA55AA; 
#10 DATA_IN <= 32'hAA55AA55; 
#10 DATA_IN <= 32'h55AA55AA; 
#10 DATA_IN <= 32'hAA55AA55; 
#10 DATA_IN <= 32'h55AA55AA; 
#10 DATA_IN <= 32'hAA55AA55; 

#10  $finish;

end 
endmodule