dled.tan.qmsg

VHDL语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register int_div:inst1\|Counter\[9\] register int_div:inst1\|Temp2 178.89 MHz 5.59 ns Internal " "Info: Clock \"clock\" has Internal fmax of 178.89 MHz between source register \"int_div:inst1\|Counter\[9\]\" and destination register \"int_div:inst1\|Temp2\" (period= 5.59 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.534 ns + Longest register register " "Info: + Longest register to register delay is 2.534 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|Counter\[9\] 1 REG LC_X28_Y13_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y13_N1; Fanout = 5; REG Node = 'int_div:inst1\|Counter\[9\]'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst1|Counter[9] } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.590 ns) 1.353 ns int_div:inst1\|Equal1~130 2 COMB LC_X29_Y13_N2 1 " "Info: 2: + IC(0.763 ns) + CELL(0.590 ns) = 1.353 ns; Loc. = LC_X29_Y13_N2; Fanout = 1; COMB Node = 'int_div:inst1\|Equal1~130'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "1.353 ns" { int_div:inst1|Counter[9] int_div:inst1|Equal1~130 } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.738 ns) 2.534 ns int_div:inst1\|Temp2 3 REG LC_X29_Y13_N5 2 " "Info: 3: + IC(0.443 ns) + CELL(0.738 ns) = 2.534 ns; Loc. = LC_X29_Y13_N5; Fanout = 2; REG Node = 'int_div:inst1\|Temp2'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "1.181 ns" { int_div:inst1|Equal1~130 int_div:inst1|Temp2 } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 52.41 % ) " "Info: Total cell delay = 1.328 ns ( 52.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.206 ns ( 47.59 % ) " "Info: Total interconnect delay = 1.206 ns ( 47.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "2.534 ns" { int_div:inst1|Counter[9] int_div:inst1|Equal1~130 int_div:inst1|Temp2 } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "2.534 ns" { int_div:inst1|Counter[9] int_div:inst1|Equal1~130 int_div:inst1|Temp2 } { 0.000ns 0.763ns 0.443ns } { 0.000ns 0.590ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.178 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dled.bdf" "" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 96 24 192 112 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns int_div:inst1\|Temp2 2 REG LC_X29_Y13_N5 2 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X29_Y13_N5; Fanout = 2; REG Node = 'int_div:inst1\|Temp2'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clock int_div:inst1|Temp2 } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clock int_div:inst1|Temp2 } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clock clock~out0 int_div:inst1|Temp2 } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.178 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dled.bdf" "" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 96 24 192 112 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns int_div:inst1\|Counter\[9\] 2 REG LC_X28_Y13_N1 5 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X28_Y13_N1; Fanout = 5; REG Node = 'int_div:inst1\|Counter\[9\]'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clock int_div:inst1|Counter[9] } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clock int_div:inst1|Counter[9] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clock clock~out0 int_div:inst1|Counter[9] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clock int_div:inst1|Temp2 } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clock clock~out0 int_div:inst1|Temp2 } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clock int_div:inst1|Counter[9] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clock clock~out0 int_div:inst1|Counter[9] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 21 -1 0 } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 17 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "2.534 ns" { int_div:inst1|Counter[9] int_div:inst1|Equal1~130 int_div:inst1|Temp2 } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "2.534 ns" { int_div:inst1|Counter[9] int_div:inst1|Equal1~130 int_div:inst1|Temp2 } { 0.000ns 0.763ns 0.443ns } { 0.000ns 0.590ns 0.738ns } "" } } { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clock int_div:inst1|Temp2 } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clock clock~out0 int_div:inst1|Temp2 } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clock int_div:inst1|Counter[9] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clock clock~out0 int_div:inst1|Counter[9] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock dig\[7\] scan_led:inst\|dig_r\[7\] 19.327 ns register " "Info: tco from clock \"clock\" to destination pin \"dig\[7\]\" through register \"scan_led:inst\|dig_r\[7\]\" is 19.327 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 10.428 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 10.428 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 18; CLK Node = 'clock'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "dled.bdf" "" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 96 24 192 112 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.935 ns) 3.402 ns int_div:inst1\|Temp2 2 REG LC_X29_Y13_N5 2 " "Info: 2: + IC(0.998 ns) + CELL(0.935 ns) = 3.402 ns; Loc. = LC_X29_Y13_N5; Fanout = 2; REG Node = 'int_div:inst1\|Temp2'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "1.933 ns" { clock int_div:inst1|Temp2 } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.292 ns) 4.470 ns int_div:inst1\|ClockOut 3 COMB LC_X28_Y13_N2 11 " "Info: 3: + IC(0.776 ns) + CELL(0.292 ns) = 4.470 ns; Loc. = LC_X28_Y13_N2; Fanout = 11; COMB Node = 'int_div:inst1\|ClockOut'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { int_div:inst1|Temp2 int_div:inst1|ClockOut } "NODE_NAME" } } { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.247 ns) + CELL(0.711 ns) 10.428 ns scan_led:inst\|dig_r\[7\] 4 REG LC_X52_Y22_N9 1 " "Info: 4: + IC(5.247 ns) + CELL(0.711 ns) = 10.428 ns; Loc. = LC_X52_Y22_N9; Fanout = 1; REG Node = 'scan_led:inst\|dig_r\[7\]'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "5.958 ns" { int_div:inst1|ClockOut scan_led:inst|dig_r[7] } "NODE_NAME" } } { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns ( 32.67 % ) " "Info: Total cell delay = 3.407 ns ( 32.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.021 ns ( 67.33 % ) " "Info: Total interconnect delay = 7.021 ns ( 67.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "10.428 ns" { clock int_div:inst1|Temp2 int_div:inst1|ClockOut scan_led:inst|dig_r[7] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "10.428 ns" { clock clock~out0 int_div:inst1|Temp2 int_div:inst1|ClockOut scan_led:inst|dig_r[7] } { 0.000ns 0.000ns 0.998ns 0.776ns 5.247ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.675 ns + Longest register pin " "Info: + Longest register to pin delay is 8.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_led:inst\|dig_r\[7\] 1 REG LC_X52_Y22_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y22_N9; Fanout = 1; REG Node = 'scan_led:inst\|dig_r\[7\]'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_led:inst|dig_r[7] } "NODE_NAME" } } { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.567 ns) + CELL(2.108 ns) 8.675 ns dig\[7\] 2 PIN PIN_239 0 " "Info: 2: + IC(6.567 ns) + CELL(2.108 ns) = 8.675 ns; Loc. = PIN_239; Fanout = 0; PIN Node = 'dig\[7\]'" {  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "8.675 ns" { scan_led:inst|dig_r[7] dig[7] } "NODE_NAME" } } { "dled.bdf" "" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 168 536 712 184 "dig\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 24.30 % ) " "Info: Total cell delay = 2.108 ns ( 24.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.567 ns ( 75.70 % ) " "Info: Total interconnect delay = 6.567 ns ( 75.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "8.675 ns" { scan_led:inst|dig_r[7] dig[7] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "8.675 ns" { scan_led:inst|dig_r[7] dig[7] } { 0.000ns 6.567ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "10.428 ns" { clock int_div:inst1|Temp2 int_div:inst1|ClockOut scan_led:inst|dig_r[7] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "10.428 ns" { clock clock~out0 int_div:inst1|Temp2 int_div:inst1|ClockOut scan_led:inst|dig_r[7] } { 0.000ns 0.000ns 0.998ns 0.776ns 5.247ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } "" } } { "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2_7_1/quartus/bin/TimingClosureFloorplan.fld" "" "8.675 ns" { scan_led:inst|dig_r[7] dig[7] } "NODE_NAME" } } { "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2_7_1/quartus/bin/Technology_Viewer.qrui" "8.675 ns" { scan_led:inst|dig_r[7] dig[7] } { 0.000ns 6.567ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "107 " "Info: Allocated 107 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 01 11:24:51 2008 " "Info: Processing ended: Mon Dec 01 11:24:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}