dled.map.qmsg

VHDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 01 11:23:51 2008 " "Info: Processing started: Mon Dec 01 11:23:51 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dled -c dled " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dled -c dled" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan_led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file scan_led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 scan_led-one " "Info: Found design unit 1: scan_led-one" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 scan_led " "Info: Found entity 1: scan_led" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-Devider " "Info: Found design unit 1: int_div-Devider" {  } { { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/int_div.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dled.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dled.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dled " "Info: Found entity 1: dled" {  } { { "dled.bdf" "" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dled " "Info: Elaborating entity \"dled\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scan_led scan_led:inst " "Info: Elaborating entity \"scan_led\" for hierarchy \"scan_led:inst\"" {  } { { "dled.bdf" "inst" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 144 376 512 240 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div int_div:inst1 " "Info: Elaborating entity \"int_div\" for hierarchy \"int_div:inst1\"" {  } { { "dled.bdf" "inst1" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 72 216 352 168 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "8constant.tdf 1 1 " "Warning: Using design file 8constant.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 8constant " "Info: Found entity 1: 8constant" {  } { { "8constant.tdf" "" { Text "D:/电子科学与技术/EDA_exp/dled/8constant.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "8constant 8constant:inst2 " "Info: Elaborating entity \"8constant\" for hierarchy \"8constant:inst2\"" {  } { { "dled.bdf" "inst2" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 240 248 326 288 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2_7_1/quartus/libraries/megafunctions/lpm_constant.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2_7_1/quartus/libraries/megafunctions/lpm_constant.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_constant " "Info: Found entity 1: lpm_constant" {  } { { "lpm_constant.tdf" "" { Text "f:/program files/quartus2_7_1/quartus/libraries/megafunctions/lpm_constant.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant 8constant:inst2\|lpm_constant:lpm_constant_component " "Info: Elaborating entity \"lpm_constant\" for hierarchy \"8constant:inst2\|lpm_constant:lpm_constant_component\"" {  } { { "8constant.tdf" "lpm_constant_component" { Text "D:/电子科学与技术/EDA_exp/dled/8constant.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "8constant:inst2\|lpm_constant:lpm_constant_component " "Info: Elaborated megafunction instantiation \"8constant:inst2\|lpm_constant:lpm_constant_component\"" {  } { { "8constant.tdf" "" { Text "D:/电子科学与技术/EDA_exp/dled/8constant.tdf" 43 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_constant_br6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_constant_br6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_constant_br6 " "Info: Found entity 1: lpm_constant_br6" {  } { { "db/lpm_constant_br6.tdf" "" { Text "D:/电子科学与技术/EDA_exp/dled/db/lpm_constant_br6.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant_br6 8constant:inst2\|lpm_constant:lpm_constant_component\|lpm_constant_br6:ag " "Info: Elaborating entity \"lpm_constant_br6\" for hierarchy \"8constant:inst2\|lpm_constant:lpm_constant_component\|lpm_constant_br6:ag\"" {  } { { "lpm_constant.tdf" "ag" { Text "f:/program files/quartus2_7_1/quartus/libraries/megafunctions/lpm_constant.tdf" 45 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "scan_led:inst\|disp_dat\[0\] scan_led:inst\|count\[0\] " "Info: Duplicate register \"scan_led:inst\|disp_dat\[0\]\" merged to single register \"scan_led:inst\|count\[0\]\"" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "scan_led:inst\|disp_dat\[3\] scan_led:inst\|dig_r\[0\] " "Info: Duplicate register \"scan_led:inst\|disp_dat\[3\]\" merged to single register \"scan_led:inst\|dig_r\[0\]\", power-up level changed" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 33 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "scan_led:inst\|count\[1\] scan_led:inst\|disp_dat\[1\] " "Info: Duplicate register \"scan_led:inst\|count\[1\]\" merged to single register \"scan_led:inst\|disp_dat\[1\]\"" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "scan_led:inst\|count\[2\] scan_led:inst\|disp_dat\[2\] " "Info: Duplicate register \"scan_led:inst\|count\[2\]\" merged to single register \"scan_led:inst\|disp_dat\[2\]\"" {  } { { "scan_led.vhd" "" { Text "D:/电子科学与技术/EDA_exp/dled/scan_led.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "dled.bdf" "" { Schematic "D:/电子科学与技术/EDA_exp/dled/dled.bdf" { { 184 536 712 200 "seg\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "62 " "Info: Implemented 62 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 01 11:24:12 2008 " "Info: Processing ended: Mon Dec 01 11:24:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}