scan_led.vhd

VHDL语言

LIBRARY IEEE;                      
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_Arith.ALL;
USE IEEE.STD_LOGIC_Unsigned.ALL;

ENTITY scan_led IS
Port
(clk_1k:in STD_LOGIC;
d:IN STD_LOGIC_vector(31 downto 0);
dig:OUT STD_LOGIC_vector(7 downto 0);
seg:out STD_LOGIC_vector(7 downto 0)           
);
END;

ARCHITECTURE  one 	OF scan_led	IS
SIGNAL	seg_r:	STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL	dig_r:	STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL	disp_dat:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL	count:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
dig<=dig_r(7 DOWNTO 0);
seg<=seg_r(7 DOWNTO 0);

PROCESS(clk_1k)
BEGIN
	IF RISING_EDGE(clk_1k) THEN
	count<=count+1;
	end if;
end PROCESS;

process(clk_1k,count)
begin
IF RISING_EDGE(clk_1k) THEN
	case count is
		when "000" => disp_dat<=d(31 downto 28);
		when "001" => disp_dat<=d(27 downto 24);
		when "010" => disp_dat<=d(23 downto 20);
		when "011" => disp_dat<=d(19 downto 16);
		when "100" => disp_dat<=d(15 downto 12);
		when "101" => disp_dat<=d(11 downto 8);
		when "110" => disp_dat<=d(7 downto 4);
		when "111" => disp_dat<=d(3 downto 0);
	end case;

	case count is
		when"000" => dig_r<="01111111";
		when"001" => dig_r<="10111111";
		when"010" => dig_r<="11011111";
		when"011" => dig_r<="11101111";
		when"100" => dig_r<="11110111";
		when"101" => dig_r<="11111011";
		when"110" => dig_r<="11111101";
		when"111" => dig_r<="11111110";
	end case;
	end if;
end process;

process(disp_dat)
begin
	case disp_dat is
		when x"0" => seg_r <=x"c0";
		when x"1" => seg_r <=x"f9";
		when x"2" => seg_r <=x"a4";
		when x"3" => seg_r <=x"b0";
		when x"4" => seg_r <=x"99";
		when x"5" => seg_r <=x"92";
		when x"6" => seg_r <=x"82";
		when x"7" => seg_r <=x"f8";
		when x"8" => seg_r <=x"80";
		when x"9" => seg_r <=x"90";
		when x"a" => seg_r <=x"88";
		when x"b" => seg_r <=x"83";
		when x"c" => seg_r <=x"c6";
		when x"d" => seg_r <=x"a1";
		when x"e" => seg_r <=x"86";
		when x"f" => seg_r <=x"8e";
	end case;
end process;
end;