📄 mult_vcs.tdf
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--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" DSP_BLOCK_BALANCING="Auto" INPUT_B_IS_CONSTANT="NO" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=13 LPM_WIDTHB=7 LPM_WIDTHP=20 LPM_WIDTHS=20 USE_EAB="OFF" clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_mult 2005:08:05:09:57:06:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_padd 2005:08:04:11:57:36:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ VERSION_END
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneii_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock)
RETURNS ( dataout[dataa_width+datab_width-1..0]);
PARAMETERS
(
dataa_width = 0
);
FUNCTION cycloneii_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
WITH ( dataa_width, output_clock)
RETURNS ( dataout[dataa_width-1..0]);
--synthesis_resources = dsp_9bit 2
SUBDESIGN mult_vcs
(
clock : input;
dataa[12..0] : input;
datab[6..0] : input;
result[19..0] : output;
)
VARIABLE
mac_mult1 : cycloneii_mac_mult
WITH (
dataa_clock = "none",
dataa_width = 13,
datab_clock = "none",
datab_width = 7,
signa_clock = "none",
signb_clock = "none"
);
mac_out2 : cycloneii_mac_out
WITH (
dataa_width = 20,
output_clock = "0"
);
aclr : NODE;
clken : NODE;
BEGIN
mac_mult1.dataa[] = ( dataa[]);
mac_mult1.datab[] = ( datab[]);
mac_mult1.signa = B"0";
mac_mult1.signb = B"0";
mac_out2.aclr = aclr;
mac_out2.clk = clock;
mac_out2.dataa[] = mac_mult1.dataout[];
mac_out2.ena = clken;
aclr = GND;
clken = VCC;
result[19..0] = mac_out2.dataout[19..0];
END;
--VALID FILE
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