log_module.map.qmsg

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component " "Info: Instantiated megafunction \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 6 " "Info: Parameter \"lpm_width\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 13 " "Info: Parameter \"lpm_widthad\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_indata REGISTERED " "Info: Parameter \"lpm_indata\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control REGISTERED " "Info: Parameter \"lpm_address_control\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata UNREGISTERED " "Info: Parameter \"lpm_outdata\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint USE_EAB=ON " "Info: Parameter \"lpm_hint\" = \"USE_EAB=ON\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(address) 12 downto 0 " "Info: Parameter \" constraint(address)\" = \"12 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(dio) 5 downto 0 " "Info: Parameter \" constraint(dio)\" = \"5 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "ram_8k_6.vhd" "" { Text "F:/xcolor/Alog/ram_8k_6.vhd" 79 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WTDFX_ASSERTION" "altram does not support Cyclone II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone II devices " "Warning: Assertion warning: altram does not support Cyclone II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone II devices" {  } { { "altram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altram.tdf" 226 2 0 } } { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 60 5 0 } } { "ram_8k_6.vhd" "" { Text "F:/xcolor/Alog/ram_8k_6.vhd" 79 -1 0 } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 170 -1 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\"" {  } { { "altram.tdf" "ram_block" { Text "d:/altera/quartus51/libraries/megafunctions/altram.tdf" 102 5 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_9l01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9l01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_9l01 " "Info: Found entity 1: altsyncram_9l01" {  } { { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 40 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_9l01 ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated " "Info: Elaborating entity \"altsyncram_9l01\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_1oa.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_1oa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_1oa " "Info: Found entity 1: decode_1oa" {  } { { "db/decode_1oa.tdf" "" { Text "F:/xcolor/Alog/db/decode_1oa.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_1oa ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|decode_1oa:decode3 " "Info: Elaborating entity \"decode_1oa\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|decode_1oa:decode3\"" {  } { { "db/altsyncram_9l01.tdf" "decode3" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 50 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_1oa ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|decode_1oa:deep_decode " "Info: Elaborating entity \"decode_1oa\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|decode_1oa:deep_decode\"" {  } { { "db/altsyncram_9l01.tdf" "deep_decode" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 51 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_fib.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_fib.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_fib " "Info: Found entity 1: mux_fib" {  } { { "db/mux_fib.tdf" "" { Text "F:/xcolor/Alog/db/mux_fib.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_fib ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|mux_fib:mux2 " "Info: Elaborating entity \"mux_fib\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|mux_fib:mux2\"" {  } { { "db/altsyncram_9l01.tdf" "mux2" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 52 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mul_13_7.vhd 2 1 " "Warning: Using design file mul_13_7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mul_13_7-SYN " "Info: Found design unit 1: mul_13_7-SYN" {  } { { "mul_13_7.vhd" "" { Text "F:/xcolor/Alog/mul_13_7.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mul_13_7 " "Info: Found entity 1: mul_13_7" {  } { { "mul_13_7.vhd" "" { Text "F:/xcolor/Alog/mul_13_7.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mul_13_7 mul_13_7:mgc_mul " "Info: Elaborating entity \"mul_13_7\" for hierarchy \"mul_13_7:mgc_mul\"" {  } { { "log_module.vhd" "mgc_mul" { Text "F:/xcolor/Alog/log_module.vhd" 182 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult mul_13_7:mgc_mul\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"mul_13_7:mgc_mul\|lpm_mult:lpm_mult_component\"" {  } { { "mul_13_7.vhd" "lpm_mult_component" { Text "F:/xcolor/Alog/mul_13_7.vhd" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_vcs.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_vcs.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_vcs " "Info: Found entity 1: mult_vcs" {  } { { "db/mult_vcs.tdf" "" { Text "F:/xcolor/Alog/db/mult_vcs.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_vcs mul_13_7:mgc_mul\|lpm_mult:lpm_mult_component\|mult_vcs:auto_generated " "Info: Elaborating entity \"mult_vcs\" for hierarchy \"mul_13_7:mgc_mul\|lpm_mult:lpm_mult_component\|mult_vcs:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 372 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[5\] " "Warning: Converting TRI node \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[5\]\" that feeds logic to a wire" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 116 9 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[4\] " "Warning: Converting TRI node \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[4\]\" that feeds logic to a wire" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 116 9 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[3\] " "Warning: Converting TRI node \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[3\]\" that feeds logic to a wire" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 116 9 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[2\] " "Warning: Converting TRI node \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[2\]\" that feeds logic to a wire" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 116 9 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[1\] " "Warning: Converting TRI node \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[1\]\" that feeds logic to a wire" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 116 9 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[0\] " "Warning: Converting TRI node \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|datatri\[0\]\" that feeds logic to a wire" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 116 9 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|log_module\|cut_down_state 4 " "Info: State machine \"\|log_module\|cut_down_state\" contains 4 states" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 39 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|log_module\|cut_down_state " "Info: Selected Auto state machine encoding method for state machine \"\|log_module\|cut_down_state\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 39 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|log_module\|cut_down_state " "Info: Encoding result for state machine \"\|log_module\|cut_down_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cut_down_state.state_3 " "Info: Encoded state bit \"cut_down_state.state_3\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cut_down_state.state_2 " "Info: Encoded state bit \"cut_down_state.state_2\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cut_down_state.state_1 " "Info: Encoded state bit \"cut_down_state.state_1\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cut_down_state.state_0 " "Info: Encoded state bit \"cut_down_state.state_0\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|log_module\|cut_down_state.state_0 0000 " "Info: State \"\|log_module\|cut_down_state.state_0\" uses code string \"0000\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|log_module\|cut_down_state.state_1 0011 " "Info: State \"\|log_module\|cut_down_state.state_1\" uses code string \"0011\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|log_module\|cut_down_state.state_2 0101 " "Info: State \"\|log_module\|cut_down_state.state_2\" uses code string \"0101\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|log_module\|cut_down_state.state_3 1001 " "Info: State \"\|log_module\|cut_down_state.state_3\" uses code string \"1001\"" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 39 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "268 " "Info: Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "24 " "Info: Implemented 24 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "223 " "Info: Implemented 223 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "2 " "Info: Implemented 2 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 22 15:24:59 2008 " "Info: Processing ended: Mon Dec 22 15:24:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}