log_module.map.qmsg

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 22 15:24:47 2008 " "Info: Processing started: Mon Dec 22 15:24:47 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off log_module -c log_module " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off log_module -c log_module" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "log_module.vhd 2 1 " "Warning: Using design file log_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 log_module-Behavioral " "Info: Found design unit 1: log_module-Behavioral" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 log_module " "Info: Found entity 1: log_module" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "log_module " "Info: Elaborating entity \"log_module\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "log_module.vhd(220) " "Info (10425): VHDL Case Statement information at log_module.vhd(220): OTHERS choice is never selected" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 220 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "add_13_13_u.vhd 2 1 " "Warning: Using design file add_13_13_u.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_13_13_u-SYN " "Info: Found design unit 1: add_13_13_u-SYN" {  } { { "add_13_13_u.vhd" "" { Text "F:/xcolor/Alog/add_13_13_u.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add_13_13_u " "Info: Found entity 1: add_13_13_u" {  } { { "add_13_13_u.vhd" "" { Text "F:/xcolor/Alog/add_13_13_u.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_13_13_u add_13_13_u:cd_add_1 " "Info: Elaborating entity \"add_13_13_u\" for hierarchy \"add_13_13_u:cd_add_1\"" {  } { { "log_module.vhd" "cd_add_1" { Text "F:/xcolor/Alog/log_module.vhd" 136 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add_13_13_u:cd_add_1\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add_13_13_u:cd_add_1\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "add_13_13_u.vhd" "lpm_add_sub_component" { Text "F:/xcolor/Alog/add_13_13_u.vhd" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_i5h.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_i5h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_i5h " "Info: Found entity 1: add_sub_i5h" {  } { { "db/add_sub_i5h.tdf" "" { Text "F:/xcolor/Alog/db/add_sub_i5h.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_i5h add_13_13_u:cd_add_1\|lpm_add_sub:lpm_add_sub_component\|add_sub_i5h:auto_generated " "Info: Elaborating entity \"add_sub_i5h\" for hierarchy \"add_13_13_u:cd_add_1\|lpm_add_sub:lpm_add_sub_component\|add_sub_i5h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 117 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "add_14_14_u.vhd 2 1 " "Warning: Using design file add_14_14_u.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_14_14_u-SYN " "Info: Found design unit 1: add_14_14_u-SYN" {  } { { "add_14_14_u.vhd" "" { Text "F:/xcolor/Alog/add_14_14_u.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add_14_14_u " "Info: Found entity 1: add_14_14_u" {  } { { "add_14_14_u.vhd" "" { Text "F:/xcolor/Alog/add_14_14_u.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_14_14_u add_14_14_u:cd_add_3 " "Info: Elaborating entity \"add_14_14_u\" for hierarchy \"add_14_14_u:cd_add_3\"" {  } { { "log_module.vhd" "cd_add_3" { Text "F:/xcolor/Alog/log_module.vhd" 156 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add_14_14_u:cd_add_3\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add_14_14_u:cd_add_3\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "add_14_14_u.vhd" "lpm_add_sub_component" { Text "F:/xcolor/Alog/add_14_14_u.vhd" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_j5h.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_j5h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_j5h " "Info: Found entity 1: add_sub_j5h" {  } { { "db/add_sub_j5h.tdf" "" { Text "F:/xcolor/Alog/db/add_sub_j5h.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_j5h add_14_14_u:cd_add_3\|lpm_add_sub:lpm_add_sub_component\|add_sub_j5h:auto_generated " "Info: Elaborating entity \"add_sub_j5h\" for hierarchy \"add_14_14_u:cd_add_3\|lpm_add_sub:lpm_add_sub_component\|add_sub_j5h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 117 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ram_8k_6.vhd 2 1 " "Warning: Using design file ram_8k_6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram_8k_6-SYN " "Info: Found design unit 1: ram_8k_6-SYN" {  } { { "ram_8k_6.vhd" "" { Text "F:/xcolor/Alog/ram_8k_6.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ram_8k_6 " "Info: Found entity 1: ram_8k_6" {  } { { "ram_8k_6.vhd" "" { Text "F:/xcolor/Alog/ram_8k_6.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_8k_6 ram_8k_6:log_data_ram " "Info: Elaborating entity \"ram_8k_6\" for hierarchy \"ram_8k_6:log_data_ram\"" {  } { { "log_module.vhd" "log_data_ram" { Text "F:/xcolor/Alog/log_module.vhd" 170 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_io " "Info: Found entity 1: lpm_ram_io" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 45 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_io ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component " "Info: Elaborating entity \"lpm_ram_io\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\"" {  } { { "ram_8k_6.vhd" "lpm_ram_io_component" { Text "F:/xcolor/Alog/ram_8k_6.vhd" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altram " "Info: Found entity 1: altram" {  } { { "altram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altram.tdf" 88 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\"" {  } { { "lpm_ram_io.tdf" "sram" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 60 5 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component " "Info: Issued messages during elaboration of megafunction \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\", which is child of megafunction \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\"" {  } { { "lpm_ram_io.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf" 60 5 0 } } { "ram_8k_6.vhd" "" { Text "F:/xcolor/Alog/ram_8k_6.vhd" 79 -1 0 } }  } 0 0 "Issued messages during elaboration of megafunction \"%1!s!\", which is child of megafunction \"%2!s!\"" 0 0}