log_module.tan.qmsg

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

{ "Info" "ITDB_TSU_RESULT" "mgc_mul_b\[0\] manual_gain\[3\] clk_5M 4.735 ns register " "Info: tsu for register \"mgc_mul_b\[0\]\" (data pin = \"manual_gain\[3\]\", clock pin = \"clk_5M\") is 4.735 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns + Longest pin register " "Info: + Longest pin to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns manual_gain\[3\] 1 PIN PIN_63 2 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_63; Fanout = 2; PIN Node = 'manual_gain\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { manual_gain[3] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.397 ns) + CELL(0.371 ns) 6.608 ns mgc_mul_b~66 2 COMB LCCOMB_X17_Y6_N0 1 " "Info: 2: + IC(5.397 ns) + CELL(0.371 ns) = 6.608 ns; Loc. = LCCOMB_X17_Y6_N0; Fanout = 1; COMB Node = 'mgc_mul_b~66'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "5.768 ns" { manual_gain[3] mgc_mul_b~66 } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.150 ns) 7.016 ns mgc_mul_b~67 3 COMB LCCOMB_X17_Y6_N28 1 " "Info: 3: + IC(0.258 ns) + CELL(0.150 ns) = 7.016 ns; Loc. = LCCOMB_X17_Y6_N28; Fanout = 1; COMB Node = 'mgc_mul_b~67'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.408 ns" { mgc_mul_b~66 mgc_mul_b~67 } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.100 ns mgc_mul_b\[0\] 4 REG LCFF_X17_Y6_N29 20 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.100 ns; Loc. = LCFF_X17_Y6_N29; Fanout = 20; REG Node = 'mgc_mul_b\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.084 ns" { mgc_mul_b~67 mgc_mul_b[0] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.445 ns ( 20.35 % ) " "Info: Total cell delay = 1.445 ns ( 20.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.655 ns ( 79.65 % ) " "Info: Total interconnect delay = 5.655 ns ( 79.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "7.100 ns" { manual_gain[3] mgc_mul_b~66 mgc_mul_b~67 mgc_mul_b[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.100 ns" { manual_gain[3] manual_gain[3]~combout mgc_mul_b~66 mgc_mul_b~67 mgc_mul_b[0] } { 0.000ns 0.000ns 5.397ns 0.258ns 0.000ns } { 0.000ns 0.840ns 0.371ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_5M destination 2.329 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_5M\" to destination register is 2.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_5M 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk_5M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_5M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_5M~clkctrl 2 COMB CLKCTRL_G2 340 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 340; COMB Node = 'clk_5M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_5M clk_5M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.537 ns) 2.329 ns mgc_mul_b\[0\] 3 REG LCFF_X17_Y6_N29 20 " "Info: 3: + IC(0.691 ns) + CELL(0.537 ns) = 2.329 ns; Loc. = LCFF_X17_Y6_N29; Fanout = 20; REG Node = 'mgc_mul_b\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.228 ns" { clk_5M~clkctrl mgc_mul_b[0] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.09 % ) " "Info: Total cell delay = 1.516 ns ( 65.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.813 ns ( 34.91 % ) " "Info: Total interconnect delay = 0.813 ns ( 34.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.329 ns" { clk_5M clk_5M~clkctrl mgc_mul_b[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.329 ns" { clk_5M clk_5M~combout clk_5M~clkctrl mgc_mul_b[0] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "7.100 ns" { manual_gain[3] mgc_mul_b~66 mgc_mul_b~67 mgc_mul_b[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.100 ns" { manual_gain[3] manual_gain[3]~combout mgc_mul_b~66 mgc_mul_b~67 mgc_mul_b[0] } { 0.000ns 0.000ns 5.397ns 0.258ns 0.000ns } { 0.000ns 0.840ns 0.371ns 0.150ns 0.084ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.329 ns" { clk_5M clk_5M~clkctrl mgc_mul_b[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.329 ns" { clk_5M clk_5M~combout clk_5M~clkctrl mgc_mul_b[0] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_5M y_out\[1\] y_out\[1\]~reg0 6.892 ns register " "Info: tco from clock \"clk_5M\" to destination pin \"y_out\[1\]\" through register \"y_out\[1\]~reg0\" is 6.892 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_5M source 2.334 ns + Longest register " "Info: + Longest clock path from clock \"clk_5M\" to source register is 2.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_5M 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk_5M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_5M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_5M~clkctrl 2 COMB CLKCTRL_G2 340 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 340; COMB Node = 'clk_5M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_5M clk_5M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.537 ns) 2.334 ns y_out\[1\]~reg0 3 REG LCFF_X15_Y5_N31 1 " "Info: 3: + IC(0.696 ns) + CELL(0.537 ns) = 2.334 ns; Loc. = LCFF_X15_Y5_N31; Fanout = 1; REG Node = 'y_out\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.233 ns" { clk_5M~clkctrl y_out[1]~reg0 } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.95 % ) " "Info: Total cell delay = 1.516 ns ( 64.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.818 ns ( 35.05 % ) " "Info: Total interconnect delay = 0.818 ns ( 35.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.334 ns" { clk_5M clk_5M~clkctrl y_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.334 ns" { clk_5M clk_5M~combout clk_5M~clkctrl y_out[1]~reg0 } { 0.000ns 0.000ns 0.122ns 0.696ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.308 ns + Longest register pin " "Info: + Longest register to pin delay is 4.308 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y_out\[1\]~reg0 1 REG LCFF_X15_Y5_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y5_N31; Fanout = 1; REG Node = 'y_out\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { y_out[1]~reg0 } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.530 ns) + CELL(2.778 ns) 4.308 ns y_out\[1\] 2 PIN PIN_129 0 " "Info: 2: + IC(1.530 ns) + CELL(2.778 ns) = 4.308 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'y_out\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "4.308 ns" { y_out[1]~reg0 y_out[1] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 264 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 64.48 % ) " "Info: Total cell delay = 2.778 ns ( 64.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.530 ns ( 35.52 % ) " "Info: Total interconnect delay = 1.530 ns ( 35.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "4.308 ns" { y_out[1]~reg0 y_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.308 ns" { y_out[1]~reg0 y_out[1] } { 0.000ns 1.530ns } { 0.000ns 2.778ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.334 ns" { clk_5M clk_5M~clkctrl y_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.334 ns" { clk_5M clk_5M~combout clk_5M~clkctrl y_out[1]~reg0 } { 0.000ns 0.000ns 0.122ns 0.696ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "4.308 ns" { y_out[1]~reg0 y_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.308 ns" { y_out[1]~reg0 y_out[1] } { 0.000ns 1.530ns } { 0.000ns 2.778ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "cutdown_reg_0\[12\] x_in\[12\] clk_20M -3.268 ns register " "Info: th for register \"cutdown_reg_0\[12\]\" (data pin = \"x_in\[12\]\", clock pin = \"clk_20M\") is -3.268 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_20M destination 2.363 ns + Longest register " "Info: + Longest clock path from clock \"clk_20M\" to destination register is 2.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_20M 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_20M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_20M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_20M~clkctrl 2 COMB CLKCTRL_G1 57 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 57; COMB Node = 'clk_20M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_20M clk_20M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.537 ns) 2.363 ns cutdown_reg_0\[12\] 3 REG LCFF_X21_Y11_N1 1 " "Info: 3: + IC(0.725 ns) + CELL(0.537 ns) = 2.363 ns; Loc. = LCFF_X21_Y11_N1; Fanout = 1; REG Node = 'cutdown_reg_0\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.262 ns" { clk_20M~clkctrl cutdown_reg_0[12] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.16 % ) " "Info: Total cell delay = 1.516 ns ( 64.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.847 ns ( 35.84 % ) " "Info: Total interconnect delay = 0.847 ns ( 35.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.363 ns" { clk_20M clk_20M~clkctrl cutdown_reg_0[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.363 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cutdown_reg_0[12] } { 0.000ns 0.000ns 0.122ns 0.725ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.897 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns x_in\[12\] 1 PIN PIN_120 4 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_120; Fanout = 4; PIN Node = 'x_in\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { x_in[12] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.824 ns) + CELL(0.149 ns) 5.813 ns cutdown_reg_0\[12\]~feeder 2 COMB LCCOMB_X21_Y11_N0 1 " "Info: 2: + IC(4.824 ns) + CELL(0.149 ns) = 5.813 ns; Loc. = LCCOMB_X21_Y11_N0; Fanout = 1; COMB Node = 'cutdown_reg_0\[12\]~feeder'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "4.973 ns" { x_in[12] cutdown_reg_0[12]~feeder } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.897 ns cutdown_reg_0\[12\] 3 REG LCFF_X21_Y11_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.897 ns; Loc. = LCFF_X21_Y11_N1; Fanout = 1; REG Node = 'cutdown_reg_0\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.084 ns" { cutdown_reg_0[12]~feeder cutdown_reg_0[12] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.073 ns ( 18.20 % ) " "Info: Total cell delay = 1.073 ns ( 18.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.824 ns ( 81.80 % ) " "Info: Total interconnect delay = 4.824 ns ( 81.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "5.897 ns" { x_in[12] cutdown_reg_0[12]~feeder cutdown_reg_0[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.897 ns" { x_in[12] x_in[12]~combout cutdown_reg_0[12]~feeder cutdown_reg_0[12] } { 0.000ns 0.000ns 4.824ns 0.000ns } { 0.000ns 0.840ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.363 ns" { clk_20M clk_20M~clkctrl cutdown_reg_0[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.363 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cutdown_reg_0[12] } { 0.000ns 0.000ns 0.122ns 0.725ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "5.897 ns" { x_in[12] cutdown_reg_0[12]~feeder cutdown_reg_0[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.897 ns" { x_in[12] x_in[12]~combout cutdown_reg_0[12]~feeder cutdown_reg_0[12] } { 0.000ns 0.000ns 4.824ns 0.000ns } { 0.000ns 0.840ns 0.149ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}