log_module.tan.qmsg

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_5M " "Info: Assuming node \"clk_5M\" is an undefined clock" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_5M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_20M " "Info: Assuming node \"clk_20M\" is an undefined clock" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_20M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_5M memory ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_address_reg0 memory ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_datain_reg0 153.05 MHz 6.534 ns Internal " "Info: Clock \"clk_5M\" has Internal fmax of 153.05 MHz between source memory \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_address_reg0\" and destination memory \"ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_datain_reg0\" (period= 6.534 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.289 ns + Longest memory memory " "Info: + Longest memory to memory delay is 6.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_address_reg0 1 MEM M4K_X23_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y7; Fanout = 1; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11 2 MEM M4K_X23_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X23_Y7; Fanout = 1; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.993 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.219 ns) + CELL(0.420 ns) 4.632 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|mux_fib:mux2\|result_node\[5\]~77 3 COMB LCCOMB_X15_Y5_N24 3 " "Info: 3: + IC(1.219 ns) + CELL(0.420 ns) = 4.632 ns; Loc. = LCCOMB_X15_Y5_N24; Fanout = 3; COMB Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|mux_fib:mux2\|result_node\[5\]~77'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.639 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 } "NODE_NAME" } "" } } { "db/mux_fib.tdf" "" { Text "F:/xcolor/Alog/db/mux_fib.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.551 ns) + CELL(0.106 ns) 6.289 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_datain_reg0 4 MEM M4K_X23_Y7 2 " "Info: 4: + IC(1.551 ns) + CELL(0.106 ns) = 6.289 ns; Loc. = M4K_X23_Y7; Fanout = 2; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_datain_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.657 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.519 ns ( 55.95 % ) " "Info: Total cell delay = 3.519 ns ( 55.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.770 ns ( 44.05 % ) " "Info: Total interconnect delay = 2.770 ns ( 44.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "6.289 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.289 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 1.219ns 1.551ns } { 0.000ns 2.993ns 0.420ns 0.106ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_5M destination 2.398 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_5M\" to destination memory is 2.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_5M 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk_5M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_5M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_5M~clkctrl 2 COMB CLKCTRL_G2 340 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 340; COMB Node = 'clk_5M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_5M clk_5M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.660 ns) 2.398 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_datain_reg0 3 MEM M4K_X23_Y7 2 " "Info: 3: + IC(0.637 ns) + CELL(0.660 ns) = 2.398 ns; Loc. = M4K_X23_Y7; Fanout = 2; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_datain_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.297 ns" { clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.639 ns ( 68.35 % ) " "Info: Total cell delay = 1.639 ns ( 68.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.759 ns ( 31.65 % ) " "Info: Total interconnect delay = 0.759 ns ( 31.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.398 ns" { clk_5M clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.398 ns" { clk_5M clk_5M~combout clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 0.122ns 0.637ns } { 0.000ns 0.979ns 0.000ns 0.660ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_5M source 2.399 ns - Longest memory " "Info: - Longest clock path from clock \"clk_5M\" to source memory is 2.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_5M 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk_5M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_5M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_5M~clkctrl 2 COMB CLKCTRL_G2 340 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 340; COMB Node = 'clk_5M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_5M clk_5M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.637 ns) + CELL(0.661 ns) 2.399 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_address_reg0 3 MEM M4K_X23_Y7 1 " "Info: 3: + IC(0.637 ns) + CELL(0.661 ns) = 2.399 ns; Loc. = M4K_X23_Y7; Fanout = 1; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a11~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.298 ns" { clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.640 ns ( 68.36 % ) " "Info: Total cell delay = 1.640 ns ( 68.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.759 ns ( 31.64 % ) " "Info: Total interconnect delay = 0.759 ns ( 31.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.399 ns" { clk_5M clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.399 ns" { clk_5M clk_5M~combout clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } { 0.000ns 0.000ns 0.122ns 0.637ns } { 0.000ns 0.979ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.398 ns" { clk_5M clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.398 ns" { clk_5M clk_5M~combout clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 0.122ns 0.637ns } { 0.000ns 0.979ns 0.000ns 0.660ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.399 ns" { clk_5M clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.399 ns" { clk_5M clk_5M~combout clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } { 0.000ns 0.000ns 0.122ns 0.637ns } { 0.000ns 0.979ns 0.000ns 0.661ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 240 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "6.289 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.289 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 1.219ns 1.551ns } { 0.000ns 2.993ns 0.420ns 0.106ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.398 ns" { clk_5M clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.398 ns" { clk_5M clk_5M~combout clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 0.122ns 0.637ns } { 0.000ns 0.979ns 0.000ns 0.660ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.399 ns" { clk_5M clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.399 ns" { clk_5M clk_5M~combout clk_5M~clkctrl ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg0 } { 0.000ns 0.000ns 0.122ns 0.637ns } { 0.000ns 0.979ns 0.000ns 0.661ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_20M register register cut_down_state.state_3 cutdown_reg_3\[13\] 420.17 MHz Internal " "Info: Clock \"clk_20M\" Internal fmax is restricted to 420.17 MHz between source register \"cut_down_state.state_3\" and destination register \"cutdown_reg_3\[13\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.423 ns + Longest register register " "Info: + Longest register to register delay is 1.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cut_down_state.state_3 1 REG LCFF_X21_Y8_N19 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N19; Fanout = 15; REG Node = 'cut_down_state.state_3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { cut_down_state.state_3 } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.660 ns) 1.423 ns cutdown_reg_3\[13\] 2 REG LCFF_X20_Y9_N7 1 " "Info: 2: + IC(0.763 ns) + CELL(0.660 ns) = 1.423 ns; Loc. = LCFF_X20_Y9_N7; Fanout = 1; REG Node = 'cutdown_reg_3\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.423 ns" { cut_down_state.state_3 cutdown_reg_3[13] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.660 ns ( 46.38 % ) " "Info: Total cell delay = 0.660 ns ( 46.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.763 ns ( 53.62 % ) " "Info: Total interconnect delay = 0.763 ns ( 53.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.423 ns" { cut_down_state.state_3 cutdown_reg_3[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.423 ns" { cut_down_state.state_3 cutdown_reg_3[13] } { 0.000ns 0.763ns } { 0.000ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_20M destination 2.352 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_20M\" to destination register is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_20M 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_20M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_20M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_20M~clkctrl 2 COMB CLKCTRL_G1 57 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 57; COMB Node = 'clk_20M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_20M clk_20M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(0.537 ns) 2.352 ns cutdown_reg_3\[13\] 3 REG LCFF_X20_Y9_N7 1 " "Info: 3: + IC(0.714 ns) + CELL(0.537 ns) = 2.352 ns; Loc. = LCFF_X20_Y9_N7; Fanout = 1; REG Node = 'cutdown_reg_3\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.251 ns" { clk_20M~clkctrl cutdown_reg_3[13] } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.46 % ) " "Info: Total cell delay = 1.516 ns ( 64.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.836 ns ( 35.54 % ) " "Info: Total interconnect delay = 0.836 ns ( 35.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.352 ns" { clk_20M clk_20M~clkctrl cutdown_reg_3[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.352 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cutdown_reg_3[13] } { 0.000ns 0.000ns 0.122ns 0.714ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_20M source 2.348 ns - Longest register " "Info: - Longest clock path from clock \"clk_20M\" to source register is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk_20M 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'clk_20M'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { clk_20M } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk_20M~clkctrl 2 COMB CLKCTRL_G1 57 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 57; COMB Node = 'clk_20M~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "0.122 ns" { clk_20M clk_20M~clkctrl } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 2.348 ns cut_down_state.state_3 3 REG LCFF_X21_Y8_N19 15 " "Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.348 ns; Loc. = LCFF_X21_Y8_N19; Fanout = 15; REG Node = 'cut_down_state.state_3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.247 ns" { clk_20M~clkctrl cut_down_state.state_3 } "NODE_NAME" } "" } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.57 % ) " "Info: Total cell delay = 1.516 ns ( 64.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.832 ns ( 35.43 % ) " "Info: Total interconnect delay = 0.832 ns ( 35.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.348 ns" { clk_20M clk_20M~clkctrl cut_down_state.state_3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.348 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cut_down_state.state_3 } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.352 ns" { clk_20M clk_20M~clkctrl cutdown_reg_3[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.352 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cutdown_reg_3[13] } { 0.000ns 0.000ns 0.122ns 0.714ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.348 ns" { clk_20M clk_20M~clkctrl cut_down_state.state_3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.348 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cut_down_state.state_3 } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.423 ns" { cut_down_state.state_3 cutdown_reg_3[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.423 ns" { cut_down_state.state_3 cutdown_reg_3[13] } { 0.000ns 0.763ns } { 0.000ns 0.660ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.352 ns" { clk_20M clk_20M~clkctrl cutdown_reg_3[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.352 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cutdown_reg_3[13] } { 0.000ns 0.000ns 0.122ns 0.714ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.348 ns" { clk_20M clk_20M~clkctrl cut_down_state.state_3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.348 ns" { clk_20M clk_20M~combout clk_20M~clkctrl cut_down_state.state_3 } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { cutdown_reg_3[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { cutdown_reg_3[13] } {  } {  } } } { "log_module.vhd" "" { Text "F:/xcolor/Alog/log_module.vhd" 199 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}