log_module.fit.qmsg

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "28 unused 3.30 21 7 0 " "Info: Number of I/O pins in group: 28 (unused VREF, 3.30 VCCIO, 21 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 5 14 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 5 total pin(s) used --  14 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 23 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 22 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  22 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 24 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.890 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 5.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a4~porta_address_reg0 1 MEM M4K_X23_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y3; Fanout = 1; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a4~porta_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 121 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a4 2 MEM M4K_X23_Y3 1 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X23_Y3; Fanout = 1; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "2.993 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 121 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.420 ns) 4.490 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|mux_fib:mux2\|result_node\[4\]~76 3 COMB LAB_X15_Y5 3 " "Info: 3: + IC(1.077 ns) + CELL(0.420 ns) = 4.490 ns; Loc. = LAB_X15_Y5; Fanout = 3; COMB Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|mux_fib:mux2\|result_node\[4\]~76'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.497 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[4]~76 } "NODE_NAME" } "" } } { "db/mux_fib.tdf" "" { Text "F:/xcolor/Alog/db/mux_fib.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.294 ns) + CELL(0.106 ns) 5.890 ns ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a4~porta_datain_reg0 4 MEM M4K_X23_Y3 2 " "Info: 4: + IC(1.294 ns) + CELL(0.106 ns) = 5.890 ns; Loc. = M4K_X23_Y3; Fanout = 2; MEM Node = 'ram_8k_6:log_data_ram\|lpm_ram_io:lpm_ram_io_component\|altram:sram\|altsyncram:ram_block\|altsyncram_9l01:auto_generated\|ram_block1a4~porta_datain_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "1.400 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[4]~76 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_9l01.tdf" "" { Text "F:/xcolor/Alog/db/altsyncram_9l01.tdf" 121 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.519 ns ( 59.75 % ) " "Info: Total cell delay = 3.519 ns ( 59.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.371 ns ( 40.25 % ) " "Info: Total interconnect delay = 2.371 ns ( 40.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "log_module" "UNKNOWN" "V1" "F:/xcolor/Alog/db/log_module.quartus_db" { Floorplan "F:/xcolor/Alog/" "" "5.890 ns" { ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4~porta_address_reg0 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[4]~76 ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4~porta_datain_reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}