log_module.hier_info

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_1oa:decode3.data[0]
address_a[12] => decode_1oa:deep_decode.data[0]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => address_reg_a[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a6.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a7.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a8.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a9.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a10.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a11.PORTADATAIN
q_a[0] <= mux_fib:mux2.result[0]
q_a[1] <= mux_fib:mux2.result[1]
q_a[2] <= mux_fib:mux2.result[2]
q_a[3] <= mux_fib:mux2.result[3]
q_a[4] <= mux_fib:mux2.result[4]
q_a[5] <= mux_fib:mux2.result[5]
wren_a => decode_1oa:decode3.enable


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|decode_1oa:decode3
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|decode_1oa:deep_decode
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE


|log_module|mul_13_7:mgc_mul
dataa[0] => lpm_mult:lpm_mult_component.dataa[0]
dataa[1] => lpm_mult:lpm_mult_component.dataa[1]
dataa[2] => lpm_mult:lpm_mult_component.dataa[2]
dataa[3] => lpm_mult:lpm_mult_component.dataa[3]
dataa[4] => lpm_mult:lpm_mult_component.dataa[4]
dataa[5] => lpm_mult:lpm_mult_component.dataa[5]
dataa[6] => lpm_mult:lpm_mult_component.dataa[6]
dataa[7] => lpm_mult:lpm_mult_component.dataa[7]
dataa[8] => lpm_mult:lpm_mult_component.dataa[8]
dataa[9] => lpm_mult:lpm_mult_component.dataa[9]
dataa[10] => lpm_mult:lpm_mult_component.dataa[10]
dataa[11] => lpm_mult:lpm_mult_component.dataa[11]
dataa[12] => lpm_mult:lpm_mult_component.dataa[12]
datab[0] => lpm_mult:lpm_mult_component.datab[0]
datab[1] => lpm_mult:lpm_mult_component.datab[1]
datab[2] => lpm_mult:lpm_mult_component.datab[2]
datab[3] => lpm_mult:lpm_mult_component.datab[3]
datab[4] => lpm_mult:lpm_mult_component.datab[4]
datab[5] => lpm_mult:lpm_mult_component.datab[5]
datab[6] => lpm_mult:lpm_mult_component.datab[6]
clock => lpm_mult:lpm_mult_component.clock
result[0] <= lpm_mult:lpm_mult_component.result[0]
result[1] <= lpm_mult:lpm_mult_component.result[1]
result[2] <= lpm_mult:lpm_mult_component.result[2]
result[3] <= lpm_mult:lpm_mult_component.result[3]
result[4] <= lpm_mult:lpm_mult_component.result[4]
result[5] <= lpm_mult:lpm_mult_component.result[5]
result[6] <= lpm_mult:lpm_mult_component.result[6]
result[7] <= lpm_mult:lpm_mult_component.result[7]
result[8] <= lpm_mult:lpm_mult_component.result[8]
result[9] <= lpm_mult:lpm_mult_component.result[9]
result[10] <= lpm_mult:lpm_mult_component.result[10]
result[11] <= lpm_mult:lpm_mult_component.result[11]
result[12] <= lpm_mult:lpm_mult_component.result[12]
result[13] <= lpm_mult:lpm_mult_component.result[13]
result[14] <= lpm_mult:lpm_mult_component.result[14]
result[15] <= lpm_mult:lpm_mult_component.result[15]
result[16] <= lpm_mult:lpm_mult_component.result[16]
result[17] <= lpm_mult:lpm_mult_component.result[17]
result[18] <= lpm_mult:lpm_mult_component.result[18]
result[19] <= lpm_mult:lpm_mult_component.result[19]


|log_module|mul_13_7:mgc_mul|lpm_mult:lpm_mult_component
dataa[0] => mult_vcs:auto_generated.dataa[0]
dataa[1] => mult_vcs:auto_generated.dataa[1]
dataa[2] => mult_vcs:auto_generated.dataa[2]
dataa[3] => mult_vcs:auto_generated.dataa[3]
dataa[4] => mult_vcs:auto_generated.dataa[4]
dataa[5] => mult_vcs:auto_generated.dataa[5]
dataa[6] => mult_vcs:auto_generated.dataa[6]
dataa[7] => mult_vcs:auto_generated.dataa[7]
dataa[8] => mult_vcs:auto_generated.dataa[8]
dataa[9] => mult_vcs:auto_generated.dataa[9]
dataa[10] => mult_vcs:auto_generated.dataa[10]
dataa[11] => mult_vcs:auto_generated.dataa[11]
dataa[12] => mult_vcs:auto_generated.dataa[12]
datab[0] => mult_vcs:auto_generated.datab[0]
datab[1] => mult_vcs:auto_generated.datab[1]
datab[2] => mult_vcs:auto_generated.datab[2]
datab[3] => mult_vcs:auto_generated.datab[3]
datab[4] => mult_vcs:auto_generated.datab[4]
datab[5] => mult_vcs:auto_generated.datab[5]
datab[6] => mult_vcs:auto_generated.datab[6]
sum[0] => ~NO_FANOUT~
sum[1] => ~NO_FANOUT~
sum[2] => ~NO_FANOUT~
sum[3] => ~NO_FANOUT~
sum[4] => ~NO_FANOUT~
sum[5] => ~NO_FANOUT~
sum[6] => ~NO_FANOUT~
sum[7] => ~NO_FANOUT~
sum[8] => ~NO_FANOUT~
sum[9] => ~NO_FANOUT~
sum[10] => ~NO_FANOUT~
sum[11] => ~NO_FANOUT~
sum[12] => ~NO_FANOUT~
sum[13] => ~NO_FANOUT~
sum[14] => ~NO_FANOUT~
sum[15] => ~NO_FANOUT~
sum[16] => ~NO_FANOUT~
sum[17] => ~NO_FANOUT~
sum[18] => ~NO_FANOUT~
sum[19] => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clock => mult_vcs:auto_generated.clock
clken => ~NO_FANOUT~
result[0] <= mult_vcs:auto_generated.result[0]
result[1] <= mult_vcs:auto_generated.result[1]
result[2] <= mult_vcs:auto_generated.result[2]
result[3] <= mult_vcs:auto_generated.result[3]
result[4] <= mult_vcs:auto_generated.result[4]
result[5] <= mult_vcs:auto_generated.result[5]
result[6] <= mult_vcs:auto_generated.result[6]
result[7] <= mult_vcs:auto_generated.result[7]
result[8] <= mult_vcs:auto_generated.result[8]
result[9] <= mult_vcs:auto_generated.result[9]
result[10] <= mult_vcs:auto_generated.result[10]
result[11] <= mult_vcs:auto_generated.result[11]
result[12] <= mult_vcs:auto_generated.result[12]
result[13] <= mult_vcs:auto_generated.result[13]
result[14] <= mult_vcs:auto_generated.result[14]
result[15] <= mult_vcs:auto_generated.result[15]
result[16] <= mult_vcs:auto_generated.result[16]
result[17] <= mult_vcs:auto_generated.result[17]
result[18] <= mult_vcs:auto_generated.result[18]
result[19] <= mult_vcs:auto_generated.result[19]


|log_module|mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated
clock => mac_out2.CLK
dataa[0] => mac_mult1.DATAA
dataa[1] => mac_mult1.DATAA1
dataa[2] => mac_mult1.DATAA2
dataa[3] => mac_mult1.DATAA3
dataa[4] => mac_mult1.DATAA4
dataa[5] => mac_mult1.DATAA5
dataa[6] => mac_mult1.DATAA6
dataa[7] => mac_mult1.DATAA7
dataa[8] => mac_mult1.DATAA8
dataa[9] => mac_mult1.DATAA9
dataa[10] => mac_mult1.DATAA10
dataa[11] => mac_mult1.DATAA11
dataa[12] => mac_mult1.DATAA12
datab[0] => mac_mult1.DATAB
datab[1] => mac_mult1.DATAB1
datab[2] => mac_mult1.DATAB2
datab[3] => mac_mult1.DATAB3
datab[4] => mac_mult1.DATAB4
datab[5] => mac_mult1.DATAB5
datab[6] => mac_mult1.DATAB6
result[0] <= mac_out2.DATAOUT
result[1] <= mac_out2.DATAOUT1
result[2] <= mac_out2.DATAOUT2
result[3] <= mac_out2.DATAOUT3
result[4] <= mac_out2.DATAOUT4
result[5] <= mac_out2.DATAOUT5
result[6] <= mac_out2.DATAOUT6
result[7] <= mac_out2.DATAOUT7
result[8] <= mac_out2.DATAOUT8
result[9] <= mac_out2.DATAOUT9
result[10] <= mac_out2.DATAOUT10
result[11] <= mac_out2.DATAOUT11
result[12] <= mac_out2.DATAOUT12
result[13] <= mac_out2.DATAOUT13
result[14] <= mac_out2.DATAOUT14
result[15] <= mac_out2.DATAOUT15
result[16] <= mac_out2.DATAOUT16
result[17] <= mac_out2.DATAOUT17
result[18] <= mac_out2.DATAOUT18
result[19] <= mac_out2.DATAOUT19