log_module.hier_info

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

clock => output_dffea[7].CLK
clock => output_dffea[6].CLK
clock => output_dffea[5].CLK
clock => output_dffea[4].CLK
clock => output_dffea[3].CLK
clock => output_dffea[2].CLK
clock => output_dffea[1].CLK
clock => output_dffea[0].CLK
cout <= cout_regr.DB_MAX_OUTPUT_PORT_TYPE
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= add_sub_cella[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= add_sub_cella[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= add_sub_cella[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= add_sub_cella[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= add_sub_cella[12].DB_MAX_OUTPUT_PORT_TYPE


|log_module|add_14_14_u:cd_add_3
dataa[0] => lpm_add_sub:lpm_add_sub_component.dataa[0]
dataa[1] => lpm_add_sub:lpm_add_sub_component.dataa[1]
dataa[2] => lpm_add_sub:lpm_add_sub_component.dataa[2]
dataa[3] => lpm_add_sub:lpm_add_sub_component.dataa[3]
dataa[4] => lpm_add_sub:lpm_add_sub_component.dataa[4]
dataa[5] => lpm_add_sub:lpm_add_sub_component.dataa[5]
dataa[6] => lpm_add_sub:lpm_add_sub_component.dataa[6]
dataa[7] => lpm_add_sub:lpm_add_sub_component.dataa[7]
dataa[8] => lpm_add_sub:lpm_add_sub_component.dataa[8]
dataa[9] => lpm_add_sub:lpm_add_sub_component.dataa[9]
dataa[10] => lpm_add_sub:lpm_add_sub_component.dataa[10]
dataa[11] => lpm_add_sub:lpm_add_sub_component.dataa[11]
dataa[12] => lpm_add_sub:lpm_add_sub_component.dataa[12]
dataa[13] => lpm_add_sub:lpm_add_sub_component.dataa[13]
datab[0] => lpm_add_sub:lpm_add_sub_component.datab[0]
datab[1] => lpm_add_sub:lpm_add_sub_component.datab[1]
datab[2] => lpm_add_sub:lpm_add_sub_component.datab[2]
datab[3] => lpm_add_sub:lpm_add_sub_component.datab[3]
datab[4] => lpm_add_sub:lpm_add_sub_component.datab[4]
datab[5] => lpm_add_sub:lpm_add_sub_component.datab[5]
datab[6] => lpm_add_sub:lpm_add_sub_component.datab[6]
datab[7] => lpm_add_sub:lpm_add_sub_component.datab[7]
datab[8] => lpm_add_sub:lpm_add_sub_component.datab[8]
datab[9] => lpm_add_sub:lpm_add_sub_component.datab[9]
datab[10] => lpm_add_sub:lpm_add_sub_component.datab[10]
datab[11] => lpm_add_sub:lpm_add_sub_component.datab[11]
datab[12] => lpm_add_sub:lpm_add_sub_component.datab[12]
datab[13] => lpm_add_sub:lpm_add_sub_component.datab[13]
clock => lpm_add_sub:lpm_add_sub_component.clock
result[0] <= lpm_add_sub:lpm_add_sub_component.result[0]
result[1] <= lpm_add_sub:lpm_add_sub_component.result[1]
result[2] <= lpm_add_sub:lpm_add_sub_component.result[2]
result[3] <= lpm_add_sub:lpm_add_sub_component.result[3]
result[4] <= lpm_add_sub:lpm_add_sub_component.result[4]
result[5] <= lpm_add_sub:lpm_add_sub_component.result[5]
result[6] <= lpm_add_sub:lpm_add_sub_component.result[6]
result[7] <= lpm_add_sub:lpm_add_sub_component.result[7]
result[8] <= lpm_add_sub:lpm_add_sub_component.result[8]
result[9] <= lpm_add_sub:lpm_add_sub_component.result[9]
result[10] <= lpm_add_sub:lpm_add_sub_component.result[10]
result[11] <= lpm_add_sub:lpm_add_sub_component.result[11]
result[12] <= lpm_add_sub:lpm_add_sub_component.result[12]
result[13] <= lpm_add_sub:lpm_add_sub_component.result[13]
cout <= lpm_add_sub:lpm_add_sub_component.cout


|log_module|add_14_14_u:cd_add_3|lpm_add_sub:lpm_add_sub_component
dataa[0] => add_sub_j5h:auto_generated.dataa[0]
dataa[1] => add_sub_j5h:auto_generated.dataa[1]
dataa[2] => add_sub_j5h:auto_generated.dataa[2]
dataa[3] => add_sub_j5h:auto_generated.dataa[3]
dataa[4] => add_sub_j5h:auto_generated.dataa[4]
dataa[5] => add_sub_j5h:auto_generated.dataa[5]
dataa[6] => add_sub_j5h:auto_generated.dataa[6]
dataa[7] => add_sub_j5h:auto_generated.dataa[7]
dataa[8] => add_sub_j5h:auto_generated.dataa[8]
dataa[9] => add_sub_j5h:auto_generated.dataa[9]
dataa[10] => add_sub_j5h:auto_generated.dataa[10]
dataa[11] => add_sub_j5h:auto_generated.dataa[11]
dataa[12] => add_sub_j5h:auto_generated.dataa[12]
dataa[13] => add_sub_j5h:auto_generated.dataa[13]
datab[0] => add_sub_j5h:auto_generated.datab[0]
datab[1] => add_sub_j5h:auto_generated.datab[1]
datab[2] => add_sub_j5h:auto_generated.datab[2]
datab[3] => add_sub_j5h:auto_generated.datab[3]
datab[4] => add_sub_j5h:auto_generated.datab[4]
datab[5] => add_sub_j5h:auto_generated.datab[5]
datab[6] => add_sub_j5h:auto_generated.datab[6]
datab[7] => add_sub_j5h:auto_generated.datab[7]
datab[8] => add_sub_j5h:auto_generated.datab[8]
datab[9] => add_sub_j5h:auto_generated.datab[9]
datab[10] => add_sub_j5h:auto_generated.datab[10]
datab[11] => add_sub_j5h:auto_generated.datab[11]
datab[12] => add_sub_j5h:auto_generated.datab[12]
datab[13] => add_sub_j5h:auto_generated.datab[13]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_j5h:auto_generated.clock
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= add_sub_j5h:auto_generated.result[0]
result[1] <= add_sub_j5h:auto_generated.result[1]
result[2] <= add_sub_j5h:auto_generated.result[2]
result[3] <= add_sub_j5h:auto_generated.result[3]
result[4] <= add_sub_j5h:auto_generated.result[4]
result[5] <= add_sub_j5h:auto_generated.result[5]
result[6] <= add_sub_j5h:auto_generated.result[6]
result[7] <= add_sub_j5h:auto_generated.result[7]
result[8] <= add_sub_j5h:auto_generated.result[8]
result[9] <= add_sub_j5h:auto_generated.result[9]
result[10] <= add_sub_j5h:auto_generated.result[10]
result[11] <= add_sub_j5h:auto_generated.result[11]
result[12] <= add_sub_j5h:auto_generated.result[12]
result[13] <= add_sub_j5h:auto_generated.result[13]
cout <= add_sub_j5h:auto_generated.cout
overflow <= <GND>


|log_module|add_14_14_u:cd_add_3|lpm_add_sub:lpm_add_sub_component|add_sub_j5h:auto_generated
clock => cout_regr.CLK
clock => output_dffea[13].CLK
clock => output_dffea[12].CLK
clock => output_dffea[11].CLK
clock => output_dffea[10].CLK
clock => output_dffea[9].CLK
clock => output_dffea[8].CLK
clock => output_dffea[7].CLK
clock => output_dffea[6].CLK
clock => output_dffea[5].CLK
clock => output_dffea[4].CLK
clock => output_dffea[3].CLK
clock => output_dffea[2].CLK
clock => output_dffea[1].CLK
clock => output_dffea[0].CLK
cout <= cout_regr.DB_MAX_OUTPUT_PORT_TYPE
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= add_sub_cella[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= add_sub_cella[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= add_sub_cella[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= add_sub_cella[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= add_sub_cella[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= add_sub_cella[13].DB_MAX_OUTPUT_PORT_TYPE


|log_module|ram_8k_6:log_data_ram
address[0] => lpm_ram_io:lpm_ram_io_component.address[0]
address[1] => lpm_ram_io:lpm_ram_io_component.address[1]
address[2] => lpm_ram_io:lpm_ram_io_component.address[2]
address[3] => lpm_ram_io:lpm_ram_io_component.address[3]
address[4] => lpm_ram_io:lpm_ram_io_component.address[4]
address[5] => lpm_ram_io:lpm_ram_io_component.address[5]
address[6] => lpm_ram_io:lpm_ram_io_component.address[6]
address[7] => lpm_ram_io:lpm_ram_io_component.address[7]
address[8] => lpm_ram_io:lpm_ram_io_component.address[8]
address[9] => lpm_ram_io:lpm_ram_io_component.address[9]
address[10] => lpm_ram_io:lpm_ram_io_component.address[10]
address[11] => lpm_ram_io:lpm_ram_io_component.address[11]
address[12] => lpm_ram_io:lpm_ram_io_component.address[12]
inclock => lpm_ram_io:lpm_ram_io_component.inclock
we => lpm_ram_io:lpm_ram_io_component.we
outenab => lpm_ram_io:lpm_ram_io_component.outenab
dio[0] <= lpm_ram_io:lpm_ram_io_component.dio[0]
dio[1] <= lpm_ram_io:lpm_ram_io_component.dio[1]
dio[2] <= lpm_ram_io:lpm_ram_io_component.dio[2]
dio[3] <= lpm_ram_io:lpm_ram_io_component.dio[3]
dio[4] <= lpm_ram_io:lpm_ram_io_component.dio[4]
dio[5] <= lpm_ram_io:lpm_ram_io_component.dio[5]


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component
dio[0] <= datatri[0]
dio[1] <= datatri[1]
dio[2] <= datatri[2]
dio[3] <= datatri[3]
dio[4] <= datatri[4]
dio[5] <= datatri[5]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
address[8] => altram:sram.address[8]
address[9] => altram:sram.address[9]
address[10] => altram:sram.address[10]
address[11] => altram:sram.address[11]
address[12] => altram:sram.address[12]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
address[0] => altsyncram:ram_block.address_a[0]
address[1] => altsyncram:ram_block.address_a[1]
address[2] => altsyncram:ram_block.address_a[2]
address[3] => altsyncram:ram_block.address_a[3]
address[4] => altsyncram:ram_block.address_a[4]
address[5] => altsyncram:ram_block.address_a[5]
address[6] => altsyncram:ram_block.address_a[6]
address[7] => altsyncram:ram_block.address_a[7]
address[8] => altsyncram:ram_block.address_a[8]
address[9] => altsyncram:ram_block.address_a[9]
address[10] => altsyncram:ram_block.address_a[10]
address[11] => altsyncram:ram_block.address_a[11]
address[12] => altsyncram:ram_block.address_a[12]
clocki => altsyncram:ram_block.clock0
clocko => ~NO_FANOUT~
q[0] <= altsyncram:ram_block.q_a[0]
q[1] <= altsyncram:ram_block.q_a[1]
q[2] <= altsyncram:ram_block.q_a[2]
q[3] <= altsyncram:ram_block.q_a[3]
q[4] <= altsyncram:ram_block.q_a[4]
q[5] <= altsyncram:ram_block.q_a[5]


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block
wren_a => altsyncram_9l01:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_9l01:auto_generated.data_a[0]
data_a[1] => altsyncram_9l01:auto_generated.data_a[1]
data_a[2] => altsyncram_9l01:auto_generated.data_a[2]
data_a[3] => altsyncram_9l01:auto_generated.data_a[3]
data_a[4] => altsyncram_9l01:auto_generated.data_a[4]
data_a[5] => altsyncram_9l01:auto_generated.data_a[5]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_9l01:auto_generated.address_a[0]
address_a[1] => altsyncram_9l01:auto_generated.address_a[1]
address_a[2] => altsyncram_9l01:auto_generated.address_a[2]
address_a[3] => altsyncram_9l01:auto_generated.address_a[3]
address_a[4] => altsyncram_9l01:auto_generated.address_a[4]
address_a[5] => altsyncram_9l01:auto_generated.address_a[5]
address_a[6] => altsyncram_9l01:auto_generated.address_a[6]
address_a[7] => altsyncram_9l01:auto_generated.address_a[7]
address_a[8] => altsyncram_9l01:auto_generated.address_a[8]
address_a[9] => altsyncram_9l01:auto_generated.address_a[9]
address_a[10] => altsyncram_9l01:auto_generated.address_a[10]
address_a[11] => altsyncram_9l01:auto_generated.address_a[11]
address_a[12] => altsyncram_9l01:auto_generated.address_a[12]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_9l01:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_9l01:auto_generated.q_a[0]
q_a[1] <= altsyncram_9l01:auto_generated.q_a[1]
q_a[2] <= altsyncram_9l01:auto_generated.q_a[2]
q_a[3] <= altsyncram_9l01:auto_generated.q_a[3]
q_a[4] <= altsyncram_9l01:auto_generated.q_a[4]
q_a[5] <= altsyncram_9l01:auto_generated.q_a[5]
q_b[0] <= <GND>


|log_module|ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3