log_module.map.rpt

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

; CBXI_PARAMETER                                 ; mult_vcs   ; Untyped                     ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                     ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                     ;
+------------------------------------------------+------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                                       ;
+---------------------------------------+----------------------------------------------+
; Name                                  ; Value                                        ;
+---------------------------------------+----------------------------------------------+
; Number of entity instances            ; 1                                            ;
; Entity Instance                       ; mul_13_7:mgc_mul|lpm_mult:lpm_mult_component ;
;     -- LPM_WIDTHA                     ; 13                                           ;
;     -- LPM_WIDTHB                     ; 7                                            ;
;     -- LPM_WIDTHP                     ; 20                                           ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                                     ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                           ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                           ;
;     -- USE_EAB                        ; OFF                                          ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                         ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                           ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                           ;
+---------------------------------------+----------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/xcolor/Alog/log_module.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 22 15:24:47 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off log_module -c log_module
Warning: Using design file log_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: log_module-Behavioral
    Info: Found entity 1: log_module
Info: Elaborating entity "log_module" for the top level hierarchy
Info (10425): VHDL Case Statement information at log_module.vhd(220): OTHERS choice is never selected
Warning: Using design file add_13_13_u.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: add_13_13_u-SYN
    Info: Found entity 1: add_13_13_u
Info: Elaborating entity "add_13_13_u" for hierarchy "add_13_13_u:cd_add_1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "add_13_13_u:cd_add_1|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_i5h.tdf
    Info: Found entity 1: add_sub_i5h
Info: Elaborating entity "add_sub_i5h" for hierarchy "add_13_13_u:cd_add_1|lpm_add_sub:lpm_add_sub_component|add_sub_i5h:auto_generated"
Warning: Using design file add_14_14_u.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: add_14_14_u-SYN
    Info: Found entity 1: add_14_14_u
Info: Elaborating entity "add_14_14_u" for hierarchy "add_14_14_u:cd_add_3"
Info: Elaborating entity "lpm_add_sub" for hierarchy "add_14_14_u:cd_add_3|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_j5h.tdf
    Info: Found entity 1: add_sub_j5h
Info: Elaborating entity "add_sub_j5h" for hierarchy "add_14_14_u:cd_add_3|lpm_add_sub:lpm_add_sub_component|add_sub_j5h:auto_generated"
Warning: Using design file ram_8k_6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ram_8k_6-SYN
    Info: Found entity 1: ram_8k_6
Info: Elaborating entity "ram_8k_6" for hierarchy "ram_8k_6:log_data_ram"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_ram_io.tdf
    Info: Found entity 1: lpm_ram_io
Info: Elaborating entity "lpm_ram_io" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altram.tdf
    Info: Found entity 1: altram
Info: Elaborating entity "altram" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram"
Info: Issued messages during elaboration of megafunction "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram", which is child of megafunction "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component"
Info: Instantiated megafunction "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component" with the following parameter:
    Info: Parameter "lpm_width" = "6"
    Info: Parameter "lpm_widthad" = "13"
    Info: Parameter "lpm_indata" = "REGISTERED"
    Info: Parameter "lpm_address_control" = "REGISTERED"
    Info: Parameter "lpm_outdata" = "UNREGISTERED"
    Info: Parameter "lpm_hint" = "USE_EAB=ON"
    Info: Parameter " constraint(address)" = "12 downto 0"
    Info: Parameter " constraint(dio)" = "5 downto 0"
Warning: Assertion warning: altram does not support Cyclone II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Cyclone II devices
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9l01.tdf
    Info: Found entity 1: altsyncram_9l01
Info: Elaborating entity "altsyncram_9l01" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/decode_1oa.tdf
    Info: Found entity 1: decode_1oa
Info: Elaborating entity "decode_1oa" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|decode_1oa:decode3"
Info: Elaborating entity "decode_1oa" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|decode_1oa:deep_decode"
Info: Found 1 design units, including 1 entities, in source file db/mux_fib.tdf
    Info: Found entity 1: mux_fib
Info: Elaborating entity "mux_fib" for hierarchy "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2"
Warning: Using design file mul_13_7.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: mul_13_7-SYN
    Info: Found entity 1: mul_13_7
Info: Elaborating entity "mul_13_7" for hierarchy "mul_13_7:mgc_mul"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "mul_13_7:mgc_mul|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_vcs.tdf
    Info: Found entity 1: mult_vcs
Info: Elaborating entity "mult_vcs" for hierarchy "mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|datatri[5]" that feeds logic to a wire
    Warning: Converting TRI node "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|datatri[4]" that feeds logic to a wire
    Warning: Converting TRI node "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|datatri[3]" that feeds logic to a wire
    Warning: Converting TRI node "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|datatri[2]" that feeds logic to a wire
    Warning: Converting TRI node "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|datatri[1]" that feeds logic to a wire
    Warning: Converting TRI node "ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|datatri[0]" that feeds logic to a wire
Info: State machine "|log_module|cut_down_state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|log_module|cut_down_state"
Info: Encoding result for state machine "|log_module|cut_down_state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "cut_down_state.state_3"
        Info: Encoded state bit "cut_down_state.state_2"
        Info: Encoded state bit "cut_down_state.state_1"
        Info: Encoded state bit "cut_down_state.state_0"
    Info: State "|log_module|cut_down_state.state_0" uses code string "0000"
    Info: State "|log_module|cut_down_state.state_1" uses code string "0011"
    Info: State "|log_module|cut_down_state.state_2" uses code string "0101"
    Info: State "|log_module|cut_down_state.state_3" uses code string "1001"
Info: Implemented 268 device resources after synthesis - the final resource count might be different
    Info: Implemented 24 input pins
    Info: Implemented 7 output pins
    Info: Implemented 223 logic cells
    Info: Implemented 12 RAM segments
    Info: Implemented 2 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Processing ended: Mon Dec 22 15:24:59 2008
    Info: Elapsed time: 00:00:13