log_module.vhd

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity log_module is
   
   -----------------------
   -- Port Declarations --
   -----------------------

   Port (
         clk_20M :         in std_logic;
         clk_5M :          in std_logic;
         reset :           in std_logic;
         x_in :            in std_logic_vector(13 downto 0);
         manual_gain :     in std_logic_vector(6 downto 0);
--   probe_select :  in std_logic_vector(1 downto 0);
         y_out :           out std_logic_vector(6 downto 0)
         );

end log_module;

architecture Behavioral of log_module is

   -- Data Cut_down States Definition
   --
   type     cut_down_states is   (
                                  state_0,
                                  state_1,
                                  state_2,
                                  state_3
                                  );
   signal   cut_down_state :     cut_down_states;

 -------------------------------------
   -- add_13_13_u Component Declaration --
   -------------------------------------

   component   add_13_13_u
      port (
            dataa		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		    datab		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		    clock		: IN STD_LOGIC ;
		    result		: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
		    cout		: OUT STD_LOGIC                    
            );
   end component;

 -------------------------------------
   -- add_14_14_u Component Declaration --
   -------------------------------------

   component   add_14_14_u
      port (
            dataa		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
		    datab		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
		    clock		: IN STD_LOGIC ;
		    result		: OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
		    cout		: OUT STD_LOGIC                   
            );
   end component;

   -------------------------------------
   -- mul_13_7 Component Declaration --
   -------------------------------------

   component   mul_13_7
      port (
            dataa		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		    datab		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		    clock		: IN STD_LOGIC ;
		    result		: OUT STD_LOGIC_VECTOR (19 DOWNTO 0)                     
            );
   end component; 

   ------------------------------------
   -- ram_8k_6 Component Declaration --
   ------------------------------------

   component   ram_8k_6
      port (
            address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		    inclock		: IN STD_LOGIC ;
		    we		    : IN STD_LOGIC  := '1';
		    outenab		: IN STD_LOGIC  := '1';
		    dio		    : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
            );
   end component;

 signal cutdown_reg_0 :std_logic_vector(13 downto 0);
 signal cutdown_reg_1 :std_logic_vector(13 downto 0);
 signal cutdown_reg_2 :std_logic_vector(13 downto 0);
 signal cutdown_reg_3 :std_logic_vector(13 downto 0);

 signal add_1_a :  std_logic_vector(12 downto 0);
 signal add_1_b :  std_logic_vector(12 downto 0);
 signal add_1_q :  std_logic_vector(13 downto 0);

 signal add_2_a :  std_logic_vector(12 downto 0);
 signal add_2_b :  std_logic_vector(12 downto 0);
 signal add_2_q :  std_logic_vector(13 downto 0); 

 signal add_3_q :  std_logic_vector(14 downto 0);

 signal cd_dv_temp_0 : std_logic;
 signal cd_dv_temp_1 : std_logic;
 signal cd_dv_temp_2 : std_logic;

   signal   data_5M :      std_logic_vector(13 downto 0);

   signal   mgc_mul_a :    std_logic_vector(12 downto 0);
   signal   mgc_mul_b :    std_logic_vector(6 downto 0);
   signal   mgc_mul_q :    std_logic_vector(19 downto 0);

   signal   ram_addr :     std_logic_vector(12 downto 0);
   signal   ram_dout :     std_logic_vector(5 downto 0);

   signal   dv_temp_1 :    std_logic;
   signal   dv_temp_2 :    std_logic;
   signal   dv_temp_3 :    std_logic;
   signal   dv_temp_4 :    std_logic;
   signal   dv_temp_5 :    std_logic;

begin

 ------------------------------
   -- Call add_13_13_u Component --
   ------------------------------

   cd_add_1:   add_13_13_u port map      (
                                        dataa => add_1_a,
		                                datab => add_1_b,
		                                clock => clk_5M,
		                                result => add_1_q(12 downto 0), 
		                                cout => add_1_q(13)              
                                        );

 cd_add_2:   add_13_13_u port map      (
                                        dataa => add_2_a,
		                                datab => add_2_b,
		                                clock => clk_5M,
		                                result => add_2_q(12 downto 0), 
		                                cout => add_2_q(13) 
                                        );

 ------------------------------
   -- Call add_14_14_u Component --
   ------------------------------

   cd_add_3:   add_14_14_u port map      (
                                        dataa => add_1_q,
		                                datab => add_2_q,
		                                clock => clk_5M,
		                                result => add_3_q(13 downto 0), 
		                                cout => add_3_q(14)      
                                        );

   -----------------------------
   -- Call ram_8k_6 Component --
   -----------------------------
  
   -- Log Data Supply RAM
   --
   log_data_ram :   ram_8k_6 port map  (
                                        address => ram_addr,
		                                inclock => clk_5M,
		                                --we	
		                                --outenab
		                                dio => ram_dout
                                        );

   -----------------------------
   -- Call mul_13_7 Component --
   -----------------------------

   mgc_mul :     mul_13_7    port map  (
                                        dataa => mgc_mul_a,
		                                datab => mgc_mul_b,
		                                clock => clk_5M,
		                                result => mgc_mul_q
                                        );


   ---------------------------
   -- Data Cut_down Process --
   ---------------------------

   process (clk_20M,reset)
  
   begin
      -- Reset
      --
      if reset = '1' then
         cutdown_reg_0 <= (others => '0');
   cutdown_reg_1 <= (others => '0');
   cutdown_reg_2 <= (others => '0');
   cutdown_reg_3 <= (others => '0');
         cut_down_state <= state_0;
           
      elsif clk_20M 'event and clk_20M = '1' then
         case cut_down_state is
            when state_0 =>
               cutdown_reg_0 <= x_in;
               cut_down_state <= state_1;
    when state_1 =>
     cutdown_reg_1 <= x_in;
               cut_down_state <= state_2;
            when state_2 =>
     cutdown_reg_2 <= x_in;
               cut_down_state <= state_3;
            when state_3 =>
     cutdown_reg_3 <= x_in;
               cut_down_state <= state_0;
            when others =>
     cutdown_reg_0 <= x_in;
               cut_down_state <= state_0;
         end case;
      end if;

   end process;

 process (clk_5M,reset)
  
   begin
      -- Reset
      --
      if reset = '1' then
   add_1_a <= (others => '0');
   add_1_b <= (others => '0');
   add_2_a <= (others => '0');
   add_2_b <= (others => '0');
   cd_dv_temp_0 <= '0';
   cd_dv_temp_1 <= '0';
   cd_dv_temp_2 <= '0';
   data_5M <= (others => '0');

  elsif clk_5M 'event and clk_5M = '1' then
   add_1_a <= cutdown_reg_0(12 downto 0);
   add_1_b <= cutdown_reg_1(12 downto 0);
   add_2_a <= cutdown_reg_2(12 downto 0);
   add_2_b <= cutdown_reg_3(12 downto 0);
   data_5M(12 downto 0) <= add_3_q(14 downto 2);
   data_5M(13) <= cd_dv_temp_2;
   cd_dv_temp_2 <= cd_dv_temp_1;
   cd_dv_temp_1 <= cd_dv_temp_0;
   cd_dv_temp_0 <= cutdown_reg_3(13);

  end if;

 end process;


   process (clk_5M,reset)
  
   begin
      -- Reset
      --
      if reset = '1' then
         mgc_mul_a <= (others => '0');
         mgc_mul_b <= (others => '0');
        
         ram_addr <= (others => '0');

         dv_temp_1 <= '0';
         dv_temp_2 <= '0';
         dv_temp_3 <= '0';
         dv_temp_4 <= '0';
         dv_temp_5 <= '0';

         y_out <= (others => '0');
           
      elsif clk_5M 'event and clk_5M = '1' then
         mgc_mul_a <= data_5M(12 downto 0);

         if manual_gain = "0000000" then
            mgc_mul_b <= "0000001";
         else
            mgc_mul_b <= manual_gain;
         end if; 

--   if probe_select = "00" then
--    if mgc_mul_q(19 downto 16) = "0000" then
--             ram_addr <= mgc_mul_q(15 downto 3);
--          else
--             ram_addr <= (others => '1');
--          end if;

--   else

         if mgc_mul_q(19 downto 17) = "000" then
            ram_addr <= mgc_mul_q(16 downto 4);
         else
            ram_addr <= (others => '1');
         end if;

--   end if;
        
         


        
         y_out(6) <= dv_temp_5;
         dv_temp_5 <= dv_temp_4;      
         dv_temp_4 <= dv_temp_3;    
         dv_temp_3 <= dv_temp_2;    
         dv_temp_2 <= dv_temp_1;    
         dv_temp_1 <= data_5M(13);        
        
         y_out(5 downto 0) <= ram_dout;      

      end if;

   end process;

end Behavioral;