log_module.tan.rpt

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                                    ; To                                                                                                                                                    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.735 ns                                       ; manual_gain[3]                                                                                                                                          ; mgc_mul_b[0]                                                                                                                                          ; --         ; clk_5M   ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 6.892 ns                                       ; y_out[1]~reg0                                                                                                                                           ; y_out[1]                                                                                                                                              ; clk_5M     ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.268 ns                                      ; x_in[12]                                                                                                                                                ; cutdown_reg_0[12]                                                                                                                                     ; --         ; clk_20M  ; 0            ;
; Clock Setup: 'clk_5M'        ; N/A   ; None          ; 153.05 MHz ( period = 6.534 ns )               ; ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_address_reg11 ; ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11~porta_datain_reg0 ; clk_5M     ; clk_5M   ; 0            ;
; Clock Setup: 'clk_20M'       ; N/A   ; None          ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cut_down_state.state_3                                                                                                                                  ; cutdown_reg_3[8]                                                                                                                                      ; clk_20M    ; clk_20M  ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                                                         ;                                                                                                                                                       ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C5T144C6        ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+