log_module.fit.eqn

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a11_PORT_A_data_in = P1L6;
M1_ram_block1a11_PORT_A_data_in_reg = DFFE(M1_ram_block1a11_PORT_A_data_in, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a11_PORT_A_address_reg = DFFE(M1_ram_block1a11_PORT_A_address, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_PORT_A_write_enable = GND;
M1_ram_block1a11_PORT_A_write_enable_reg = DFFE(M1_ram_block1a11_PORT_A_write_enable, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_clock_0 = GLOBAL(A1L104);
M1_ram_block1a11_clock_enable_0 = ram_addr[12];
M1_ram_block1a11_PORT_A_data_out = MEMORY(M1_ram_block1a11_PORT_A_data_in_reg, , M1_ram_block1a11_PORT_A_address_reg, , M1_ram_block1a11_PORT_A_write_enable_reg, , , , M1_ram_block1a11_clock_0, , M1_ram_block1a11_clock_enable_0, , , );
M1_ram_block1a11 = M1_ram_block1a11_PORT_A_data_out[0];


--M1_ram_block1a5 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a5 at M4K_X23_Y5
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a5_PORT_A_data_in = P1L6;
M1_ram_block1a5_PORT_A_data_in_reg = DFFE(M1_ram_block1a5_PORT_A_data_in, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a5_PORT_A_address_reg = DFFE(M1_ram_block1a5_PORT_A_address, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_PORT_A_write_enable = GND;
M1_ram_block1a5_PORT_A_write_enable_reg = DFFE(M1_ram_block1a5_PORT_A_write_enable, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_clock_0 = GLOBAL(A1L104);
M1_ram_block1a5_clock_enable_0 = !ram_addr[12];
M1_ram_block1a5_PORT_A_data_out = MEMORY(M1_ram_block1a5_PORT_A_data_in_reg, , M1_ram_block1a5_PORT_A_address_reg, , M1_ram_block1a5_PORT_A_write_enable_reg, , , , M1_ram_block1a5_clock_0, , M1_ram_block1a5_clock_enable_0, , , );
M1_ram_block1a5 = M1_ram_block1a5_PORT_A_data_out[0];


--P1L6 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77 at LCCOMB_X15_Y5_N24
P1L6 = M1_address_reg_a[0] & (M1_ram_block1a11) # !M1_address_reg_a[0] & M1_ram_block1a5;


--dv_temp_5 is dv_temp_5 at LCFF_X13_Y9_N7
dv_temp_5 = DFFEAS(A1L236, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[12] is ram_addr[12] at LCFF_X15_Y5_N15
ram_addr[12] = DFFEAS(A1L297, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[0] is ram_addr[0] at LCFF_X15_Y5_N7
ram_addr[0] = DFFEAS(A1L298, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[1] is ram_addr[1] at LCFF_X15_Y5_N5
ram_addr[1] = DFFEAS(A1L299, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[2] is ram_addr[2] at LCFF_X15_Y5_N19
ram_addr[2] = DFFEAS(A1L300, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[3] is ram_addr[3] at LCFF_X15_Y5_N3
ram_addr[3] = DFFEAS(A1L301, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[4] is ram_addr[4] at LCFF_X15_Y5_N27
ram_addr[4] = DFFEAS(A1L302, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[5] is ram_addr[5] at LCFF_X15_Y5_N21
ram_addr[5] = DFFEAS(A1L303, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[6] is ram_addr[6] at LCFF_X15_Y5_N9
ram_addr[6] = DFFEAS(A1L304, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[7] is ram_addr[7] at LCFF_X15_Y5_N11
ram_addr[7] = DFFEAS(A1L305, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[8] is ram_addr[8] at LCFF_X15_Y6_N19
ram_addr[8] = DFFEAS(A1L306, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[9] is ram_addr[9] at LCFF_X15_Y6_N21
ram_addr[9] = DFFEAS(A1L307, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[10] is ram_addr[10] at LCFF_X15_Y6_N3
ram_addr[10] = DFFEAS(A1L308, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--ram_addr[11] is ram_addr[11] at LCFF_X15_Y6_N23
ram_addr[11] = DFFEAS(A1L309, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--dv_temp_4 is dv_temp_4 at LCFF_X13_Y9_N11
dv_temp_4 = DFFEAS(A1L234, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--R1_result[4] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[4] at DSPOUT_X16_Y6_N2
--DSP Block Operation Mode: Simple Multiplier (18-bit)
R1_result[4] = DFFE(R1L21, GLOBAL(A1L104), , , );

--R1_result[5] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[5] at DSPOUT_X16_Y6_N2
R1_result[5] = DFFE(R1L22, GLOBAL(A1L104), , , );

--R1_result[6] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[6] at DSPOUT_X16_Y6_N2
R1_result[6] = DFFE(R1L23, GLOBAL(A1L104), , , );

--R1_result[7] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[7] at DSPOUT_X16_Y6_N2
R1_result[7] = DFFE(R1L24, GLOBAL(A1L104), , , );

--R1_result[8] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[8] at DSPOUT_X16_Y6_N2
R1_result[8] = DFFE(R1L25, GLOBAL(A1L104), , , );

--R1_result[9] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[9] at DSPOUT_X16_Y6_N2
R1_result[9] = DFFE(R1L26, GLOBAL(A1L104), , , );

--R1_result[10] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[10] at DSPOUT_X16_Y6_N2
R1_result[10] = DFFE(R1L27, GLOBAL(A1L104), , , );

--R1_result[11] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[11] at DSPOUT_X16_Y6_N2
R1_result[11] = DFFE(R1L28, GLOBAL(A1L104), , , );

--R1_result[12] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[12] at DSPOUT_X16_Y6_N2
R1_result[12] = DFFE(R1L29, GLOBAL(A1L104), , , );

--R1_result[13] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[13] at DSPOUT_X16_Y6_N2
R1_result[13] = DFFE(R1L30, GLOBAL(A1L104), , , );

--R1_result[14] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[14] at DSPOUT_X16_Y6_N2
R1_result[14] = DFFE(R1L31, GLOBAL(A1L104), , , );

--R1_result[15] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[15] at DSPOUT_X16_Y6_N2
R1_result[15] = DFFE(R1L32, GLOBAL(A1L104), , , );

--R1_result[16] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[16] at DSPOUT_X16_Y6_N2
R1_result[16] = DFFE(R1L33, GLOBAL(A1L104), , , );

--R1_result[17] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[17] at DSPOUT_X16_Y6_N2
R1_result[17] = DFFE(R1L34, GLOBAL(A1L104), , , );

--R1_result[18] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[18] at DSPOUT_X16_Y6_N2
R1_result[18] = DFFE(R1L35, GLOBAL(A1L104), , , );

--R1_result[19] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[19] at DSPOUT_X16_Y6_N2
R1_result[19] = DFFE(R1L36, GLOBAL(A1L104), , , );


--A1L297 is ram_addr~143 at LCCOMB_X15_Y5_N14
A1L297 = R1_result[17] # R1_result[16] # R1_result[19] # R1_result[18];


--A1L298 is ram_addr~144 at LCCOMB_X15_Y5_N6
A1L298 = R1_result[17] # R1_result[4] # R1_result[19] # R1_result[18];


--A1L299 is ram_addr~145 at LCCOMB_X15_Y5_N4
A1L299 = R1_result[17] # R1_result[5] # R1_result[19] # R1_result[18];


--A1L300 is ram_addr~146 at LCCOMB_X15_Y5_N18
A1L300 = R1_result[17] # R1_result[6] # R1_result[19] # R1_result[18];


--A1L301 is ram_addr~147 at LCCOMB_X15_Y5_N2
A1L301 = R1_result[17] # R1_result[7] # R1_result[19] # R1_result[18];


--A1L302 is ram_addr~148 at LCCOMB_X15_Y5_N26
A1L302 = R1_result[17] # R1_result[8] # R1_result[19] # R1_result[18];


--A1L303 is ram_addr~149 at LCCOMB_X15_Y5_N20
A1L303 = R1_result[17] # R1_result[9] # R1_result[19] # R1_result[18];


--A1L304 is ram_addr~150 at LCCOMB_X15_Y5_N8
A1L304 = R1_result[17] # R1_result[10] # R1_result[19] # R1_result[18];


--A1L305 is ram_addr~151 at LCCOMB_X15_Y5_N10
A1L305 = R1_result[17] # R1_result[11] # R1_result[19] # R1_result[18];


--A1L306 is ram_addr~152 at LCCOMB_X15_Y6_N18
A1L306 = R1_result[12] # R1_result[17] # R1_result[19] # R1_result[18];


--A1L307 is ram_addr~153 at LCCOMB_X15_Y6_N20
A1L307 = R1_result[18] # R1_result[19] # R1_result[13] # R1_result[17];


--A1L308 is ram_addr~154 at LCCOMB_X15_Y6_N2
A1L308 = R1_result[18] # R1_result[17] # R1_result[19] # R1_result[14];


--A1L309 is ram_addr~155 at LCCOMB_X15_Y6_N22
A1L309 = R1_result[18] # R1_result[19] # R1_result[15] # R1_result[17];


--dv_temp_3 is dv_temp_3 at LCFF_X13_Y9_N23
dv_temp_3 = DFFEAS(A1L232, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--R1_mac_mult1 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1 at DSPMULT_X16_Y6_N0
--DSP Block Multiplier Base Width: 18-bits
R1_mac_mult1_a_data = DATA(mgc_mul_a[12], mgc_mul_a[11], mgc_mul_a[10], mgc_mul_a[9], mgc_mul_a[8], mgc_mul_a[7], mgc_mul_a[6], mgc_mul_a[5], mgc_mul_a[4], mgc_mul_a[3], mgc_mul_a[2], mgc_mul_a[1], mgc_mul_a[0]);
R1_mac_mult1_a_rep = ~GND ? SIGNED(R1_mac_mult1_a_data) : UNSIGNED(R1_mac_mult1_a_data);
R1_mac_mult1_b_data = DATA(mgc_mul_b[6], mgc_mul_b[5], mgc_mul_b[4], mgc_mul_b[3], mgc_mul_b[2], mgc_mul_b[1], mgc_mul_b[0]);
R1_mac_mult1_b_rep = ~GND ? SIGNED(R1_mac_mult1_b_data) : UNSIGNED(R1_mac_mult1_b_data);
R1_mac_mult1_result = R1_mac_mult1_a_rep * R1_mac_mult1_b_rep;
R1_mac_mult1 = R1_mac_mult1_result[0];

--R1L18 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT1 at DSPMULT_X16_Y6_N0
R1L18 = R1_mac_mult1_result[1];

--R1L19 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT2 at DSPMULT_X16_Y6_N0
R1L19 = R1_mac_mult1_result[2];

--R1L20 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT3 at DSPMULT_X16_Y6_N0
R1L20 = R1_mac_mult1_result[3];

--R1L21 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT4 at DSPMULT_X16_Y6_N0
R1L21 = R1_mac_mult1_result[4];

--R1L22 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT5 at DSPMULT_X16_Y6_N0
R1L22 = R1_mac_mult1_result[5];

--R1L23 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT6 at DSPMULT_X16_Y6_N0
R1L23 = R1_mac_mult1_result[6];

--R1L24 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT7 at DSPMULT_X16_Y6_N0
R1L24 = R1_mac_mult1_result[7];

--R1L25 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT8 at DSPMULT_X16_Y6_N0
R1L25 = R1_mac_mult1_result[8];

--R1L26 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT9 at DSPMULT_X16_Y6_N0
R1L26 = R1_mac_mult1_result[9];

--R1L27 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT10 at DSPMULT_X16_Y6_N0
R1L27 = R1_mac_mult1_result[10];