log_module.fit.eqn

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L329Q is y_out[0]~reg0 at LCFF_X15_Y5_N29
A1L329Q = DFFEAS(P1L1, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--A1L331Q is y_out[1]~reg0 at LCFF_X15_Y5_N31
A1L331Q = DFFEAS(P1L2, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--A1L333Q is y_out[2]~reg0 at LCFF_X15_Y5_N13
A1L333Q = DFFEAS(P1L3, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--A1L335Q is y_out[3]~reg0 at LCFF_X15_Y5_N17
A1L335Q = DFFEAS(P1L4, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--A1L337Q is y_out[4]~reg0 at LCFF_X15_Y5_N23
A1L337Q = DFFEAS(P1L5, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--A1L339Q is y_out[5]~reg0 at LCFF_X15_Y5_N25
A1L339Q = DFFEAS(P1L6, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--A1L341Q is y_out[6]~reg0 at LCFF_X13_Y9_N1
A1L341Q = DFFEAS(A1L342, GLOBAL(A1L104), !GLOBAL(A1L311),  ,  ,  ,  ,  ,  );


--M1_ram_block1a6 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a6 at M4K_X11_Y5
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a6_PORT_A_data_in = P1L1;
M1_ram_block1a6_PORT_A_data_in_reg = DFFE(M1_ram_block1a6_PORT_A_data_in, M1_ram_block1a6_clock_0, , , M1_ram_block1a6_clock_enable_0);
M1_ram_block1a6_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a6_PORT_A_address_reg = DFFE(M1_ram_block1a6_PORT_A_address, M1_ram_block1a6_clock_0, , , M1_ram_block1a6_clock_enable_0);
M1_ram_block1a6_PORT_A_write_enable = GND;
M1_ram_block1a6_PORT_A_write_enable_reg = DFFE(M1_ram_block1a6_PORT_A_write_enable, M1_ram_block1a6_clock_0, , , M1_ram_block1a6_clock_enable_0);
M1_ram_block1a6_clock_0 = GLOBAL(A1L104);
M1_ram_block1a6_clock_enable_0 = ram_addr[12];
M1_ram_block1a6_PORT_A_data_out = MEMORY(M1_ram_block1a6_PORT_A_data_in_reg, , M1_ram_block1a6_PORT_A_address_reg, , M1_ram_block1a6_PORT_A_write_enable_reg, , , , M1_ram_block1a6_clock_0, , M1_ram_block1a6_clock_enable_0, , , );
M1_ram_block1a6 = M1_ram_block1a6_PORT_A_data_out[0];


--M1_ram_block1a0 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a0 at M4K_X11_Y4
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a0_PORT_A_data_in = P1L1;
M1_ram_block1a0_PORT_A_data_in_reg = DFFE(M1_ram_block1a0_PORT_A_data_in, M1_ram_block1a0_clock_0, , , M1_ram_block1a0_clock_enable_0);
M1_ram_block1a0_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a0_PORT_A_address_reg = DFFE(M1_ram_block1a0_PORT_A_address, M1_ram_block1a0_clock_0, , , M1_ram_block1a0_clock_enable_0);
M1_ram_block1a0_PORT_A_write_enable = GND;
M1_ram_block1a0_PORT_A_write_enable_reg = DFFE(M1_ram_block1a0_PORT_A_write_enable, M1_ram_block1a0_clock_0, , , M1_ram_block1a0_clock_enable_0);
M1_ram_block1a0_clock_0 = GLOBAL(A1L104);
M1_ram_block1a0_clock_enable_0 = !ram_addr[12];
M1_ram_block1a0_PORT_A_data_out = MEMORY(M1_ram_block1a0_PORT_A_data_in_reg, , M1_ram_block1a0_PORT_A_address_reg, , M1_ram_block1a0_PORT_A_write_enable_reg, , , , M1_ram_block1a0_clock_0, , M1_ram_block1a0_clock_enable_0, , , );
M1_ram_block1a0 = M1_ram_block1a0_PORT_A_data_out[0];


--M1_address_reg_a[0] is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|address_reg_a[0] at LCFF_X15_Y5_N1
M1_address_reg_a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L104),  ,  ,  , ram_addr[12],  ,  , VCC);


--P1L1 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[0]~72 at LCCOMB_X15_Y5_N28
P1L1 = M1_address_reg_a[0] & (M1_ram_block1a6) # !M1_address_reg_a[0] & M1_ram_block1a0;


--M1_ram_block1a7 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a7 at M4K_X11_Y8
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a7_PORT_A_data_in = P1L2;
M1_ram_block1a7_PORT_A_data_in_reg = DFFE(M1_ram_block1a7_PORT_A_data_in, M1_ram_block1a7_clock_0, , , M1_ram_block1a7_clock_enable_0);
M1_ram_block1a7_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a7_PORT_A_address_reg = DFFE(M1_ram_block1a7_PORT_A_address, M1_ram_block1a7_clock_0, , , M1_ram_block1a7_clock_enable_0);
M1_ram_block1a7_PORT_A_write_enable = GND;
M1_ram_block1a7_PORT_A_write_enable_reg = DFFE(M1_ram_block1a7_PORT_A_write_enable, M1_ram_block1a7_clock_0, , , M1_ram_block1a7_clock_enable_0);
M1_ram_block1a7_clock_0 = GLOBAL(A1L104);
M1_ram_block1a7_clock_enable_0 = ram_addr[12];
M1_ram_block1a7_PORT_A_data_out = MEMORY(M1_ram_block1a7_PORT_A_data_in_reg, , M1_ram_block1a7_PORT_A_address_reg, , M1_ram_block1a7_PORT_A_write_enable_reg, , , , M1_ram_block1a7_clock_0, , M1_ram_block1a7_clock_enable_0, , , );
M1_ram_block1a7 = M1_ram_block1a7_PORT_A_data_out[0];


--M1_ram_block1a1 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a1 at M4K_X11_Y9
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a1_PORT_A_data_in = P1L2;
M1_ram_block1a1_PORT_A_data_in_reg = DFFE(M1_ram_block1a1_PORT_A_data_in, M1_ram_block1a1_clock_0, , , M1_ram_block1a1_clock_enable_0);
M1_ram_block1a1_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a1_PORT_A_address_reg = DFFE(M1_ram_block1a1_PORT_A_address, M1_ram_block1a1_clock_0, , , M1_ram_block1a1_clock_enable_0);
M1_ram_block1a1_PORT_A_write_enable = GND;
M1_ram_block1a1_PORT_A_write_enable_reg = DFFE(M1_ram_block1a1_PORT_A_write_enable, M1_ram_block1a1_clock_0, , , M1_ram_block1a1_clock_enable_0);
M1_ram_block1a1_clock_0 = GLOBAL(A1L104);
M1_ram_block1a1_clock_enable_0 = !ram_addr[12];
M1_ram_block1a1_PORT_A_data_out = MEMORY(M1_ram_block1a1_PORT_A_data_in_reg, , M1_ram_block1a1_PORT_A_address_reg, , M1_ram_block1a1_PORT_A_write_enable_reg, , , , M1_ram_block1a1_clock_0, , M1_ram_block1a1_clock_enable_0, , , );
M1_ram_block1a1 = M1_ram_block1a1_PORT_A_data_out[0];


--P1L2 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[1]~73 at LCCOMB_X15_Y5_N30
P1L2 = M1_address_reg_a[0] & (M1_ram_block1a7) # !M1_address_reg_a[0] & M1_ram_block1a1;


--M1_ram_block1a8 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a8 at M4K_X11_Y7
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a8_PORT_A_data_in = P1L3;
M1_ram_block1a8_PORT_A_data_in_reg = DFFE(M1_ram_block1a8_PORT_A_data_in, M1_ram_block1a8_clock_0, , , M1_ram_block1a8_clock_enable_0);
M1_ram_block1a8_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a8_PORT_A_address_reg = DFFE(M1_ram_block1a8_PORT_A_address, M1_ram_block1a8_clock_0, , , M1_ram_block1a8_clock_enable_0);
M1_ram_block1a8_PORT_A_write_enable = GND;
M1_ram_block1a8_PORT_A_write_enable_reg = DFFE(M1_ram_block1a8_PORT_A_write_enable, M1_ram_block1a8_clock_0, , , M1_ram_block1a8_clock_enable_0);
M1_ram_block1a8_clock_0 = GLOBAL(A1L104);
M1_ram_block1a8_clock_enable_0 = ram_addr[12];
M1_ram_block1a8_PORT_A_data_out = MEMORY(M1_ram_block1a8_PORT_A_data_in_reg, , M1_ram_block1a8_PORT_A_address_reg, , M1_ram_block1a8_PORT_A_write_enable_reg, , , , M1_ram_block1a8_clock_0, , M1_ram_block1a8_clock_enable_0, , , );
M1_ram_block1a8 = M1_ram_block1a8_PORT_A_data_out[0];


--M1_ram_block1a2 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a2 at M4K_X11_Y6
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a2_PORT_A_data_in = P1L3;
M1_ram_block1a2_PORT_A_data_in_reg = DFFE(M1_ram_block1a2_PORT_A_data_in, M1_ram_block1a2_clock_0, , , M1_ram_block1a2_clock_enable_0);
M1_ram_block1a2_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a2_PORT_A_address_reg = DFFE(M1_ram_block1a2_PORT_A_address, M1_ram_block1a2_clock_0, , , M1_ram_block1a2_clock_enable_0);
M1_ram_block1a2_PORT_A_write_enable = GND;
M1_ram_block1a2_PORT_A_write_enable_reg = DFFE(M1_ram_block1a2_PORT_A_write_enable, M1_ram_block1a2_clock_0, , , M1_ram_block1a2_clock_enable_0);
M1_ram_block1a2_clock_0 = GLOBAL(A1L104);
M1_ram_block1a2_clock_enable_0 = !ram_addr[12];
M1_ram_block1a2_PORT_A_data_out = MEMORY(M1_ram_block1a2_PORT_A_data_in_reg, , M1_ram_block1a2_PORT_A_address_reg, , M1_ram_block1a2_PORT_A_write_enable_reg, , , , M1_ram_block1a2_clock_0, , M1_ram_block1a2_clock_enable_0, , , );
M1_ram_block1a2 = M1_ram_block1a2_PORT_A_data_out[0];


--P1L3 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[2]~74 at LCCOMB_X15_Y5_N12
P1L3 = M1_address_reg_a[0] & (M1_ram_block1a8) # !M1_address_reg_a[0] & M1_ram_block1a2;


--M1_ram_block1a9 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a9 at M4K_X23_Y6
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a9_PORT_A_data_in = P1L4;
M1_ram_block1a9_PORT_A_data_in_reg = DFFE(M1_ram_block1a9_PORT_A_data_in, M1_ram_block1a9_clock_0, , , M1_ram_block1a9_clock_enable_0);
M1_ram_block1a9_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a9_PORT_A_address_reg = DFFE(M1_ram_block1a9_PORT_A_address, M1_ram_block1a9_clock_0, , , M1_ram_block1a9_clock_enable_0);
M1_ram_block1a9_PORT_A_write_enable = GND;
M1_ram_block1a9_PORT_A_write_enable_reg = DFFE(M1_ram_block1a9_PORT_A_write_enable, M1_ram_block1a9_clock_0, , , M1_ram_block1a9_clock_enable_0);
M1_ram_block1a9_clock_0 = GLOBAL(A1L104);
M1_ram_block1a9_clock_enable_0 = ram_addr[12];
M1_ram_block1a9_PORT_A_data_out = MEMORY(M1_ram_block1a9_PORT_A_data_in_reg, , M1_ram_block1a9_PORT_A_address_reg, , M1_ram_block1a9_PORT_A_write_enable_reg, , , , M1_ram_block1a9_clock_0, , M1_ram_block1a9_clock_enable_0, , , );
M1_ram_block1a9 = M1_ram_block1a9_PORT_A_data_out[0];


--M1_ram_block1a3 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a3 at M4K_X23_Y4
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a3_PORT_A_data_in = P1L4;
M1_ram_block1a3_PORT_A_data_in_reg = DFFE(M1_ram_block1a3_PORT_A_data_in, M1_ram_block1a3_clock_0, , , M1_ram_block1a3_clock_enable_0);
M1_ram_block1a3_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a3_PORT_A_address_reg = DFFE(M1_ram_block1a3_PORT_A_address, M1_ram_block1a3_clock_0, , , M1_ram_block1a3_clock_enable_0);
M1_ram_block1a3_PORT_A_write_enable = GND;
M1_ram_block1a3_PORT_A_write_enable_reg = DFFE(M1_ram_block1a3_PORT_A_write_enable, M1_ram_block1a3_clock_0, , , M1_ram_block1a3_clock_enable_0);
M1_ram_block1a3_clock_0 = GLOBAL(A1L104);
M1_ram_block1a3_clock_enable_0 = !ram_addr[12];
M1_ram_block1a3_PORT_A_data_out = MEMORY(M1_ram_block1a3_PORT_A_data_in_reg, , M1_ram_block1a3_PORT_A_address_reg, , M1_ram_block1a3_PORT_A_write_enable_reg, , , , M1_ram_block1a3_clock_0, , M1_ram_block1a3_clock_enable_0, , , );
M1_ram_block1a3 = M1_ram_block1a3_PORT_A_data_out[0];


--P1L4 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[3]~75 at LCCOMB_X15_Y5_N16
P1L4 = M1_address_reg_a[0] & M1_ram_block1a9 # !M1_address_reg_a[0] & (M1_ram_block1a3);


--M1_ram_block1a10 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a10 at M4K_X11_Y3
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a10_PORT_A_data_in = P1L5;
M1_ram_block1a10_PORT_A_data_in_reg = DFFE(M1_ram_block1a10_PORT_A_data_in, M1_ram_block1a10_clock_0, , , M1_ram_block1a10_clock_enable_0);
M1_ram_block1a10_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a10_PORT_A_address_reg = DFFE(M1_ram_block1a10_PORT_A_address, M1_ram_block1a10_clock_0, , , M1_ram_block1a10_clock_enable_0);
M1_ram_block1a10_PORT_A_write_enable = GND;
M1_ram_block1a10_PORT_A_write_enable_reg = DFFE(M1_ram_block1a10_PORT_A_write_enable, M1_ram_block1a10_clock_0, , , M1_ram_block1a10_clock_enable_0);
M1_ram_block1a10_clock_0 = GLOBAL(A1L104);
M1_ram_block1a10_clock_enable_0 = ram_addr[12];
M1_ram_block1a10_PORT_A_data_out = MEMORY(M1_ram_block1a10_PORT_A_data_in_reg, , M1_ram_block1a10_PORT_A_address_reg, , M1_ram_block1a10_PORT_A_write_enable_reg, , , , M1_ram_block1a10_clock_0, , M1_ram_block1a10_clock_enable_0, , , );
M1_ram_block1a10 = M1_ram_block1a10_PORT_A_data_out[0];


--M1_ram_block1a4 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a4 at M4K_X23_Y3
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a4_PORT_A_data_in = P1L5;
M1_ram_block1a4_PORT_A_data_in_reg = DFFE(M1_ram_block1a4_PORT_A_data_in, M1_ram_block1a4_clock_0, , , M1_ram_block1a4_clock_enable_0);
M1_ram_block1a4_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a4_PORT_A_address_reg = DFFE(M1_ram_block1a4_PORT_A_address, M1_ram_block1a4_clock_0, , , M1_ram_block1a4_clock_enable_0);
M1_ram_block1a4_PORT_A_write_enable = GND;
M1_ram_block1a4_PORT_A_write_enable_reg = DFFE(M1_ram_block1a4_PORT_A_write_enable, M1_ram_block1a4_clock_0, , , M1_ram_block1a4_clock_enable_0);
M1_ram_block1a4_clock_0 = GLOBAL(A1L104);
M1_ram_block1a4_clock_enable_0 = !ram_addr[12];
M1_ram_block1a4_PORT_A_data_out = MEMORY(M1_ram_block1a4_PORT_A_data_in_reg, , M1_ram_block1a4_PORT_A_address_reg, , M1_ram_block1a4_PORT_A_write_enable_reg, , , , M1_ram_block1a4_clock_0, , M1_ram_block1a4_clock_enable_0, , , );
M1_ram_block1a4 = M1_ram_block1a4_PORT_A_data_out[0];


--P1L5 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[4]~76 at LCCOMB_X15_Y5_N22
P1L5 = M1_address_reg_a[0] & M1_ram_block1a10 # !M1_address_reg_a[0] & (M1_ram_block1a4);


--M1_ram_block1a11 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a11 at M4K_X23_Y7
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6