log_module.map.eqn

用于实现超声回波数据的对数压缩处理,用ALTERA QUARTUSII5.1以上版本软件可以打开

--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a11_PORT_A_data_in = P1L6;
M1_ram_block1a11_PORT_A_data_in_reg = DFFE(M1_ram_block1a11_PORT_A_data_in, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a11_PORT_A_address_reg = DFFE(M1_ram_block1a11_PORT_A_address, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_PORT_B_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a11_PORT_B_address_reg = DFFE(M1_ram_block1a11_PORT_B_address, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_PORT_A_write_enable = GND;
M1_ram_block1a11_PORT_A_write_enable_reg = DFFE(M1_ram_block1a11_PORT_A_write_enable, M1_ram_block1a11_clock_0, , , M1_ram_block1a11_clock_enable_0);
M1_ram_block1a11_clock_0 = clk_5M;
M1_ram_block1a11_clock_enable_0 = ram_addr[12];
M1_ram_block1a11_PORT_A_data_out = MEMORY(M1_ram_block1a11_PORT_A_data_in_reg, , M1_ram_block1a11_PORT_A_address_reg, M1_ram_block1a11_PORT_B_address_reg, M1_ram_block1a11_PORT_A_write_enable_reg, , , , M1_ram_block1a11_clock_0, , M1_ram_block1a11_clock_enable_0, , , );
M1_ram_block1a11 = M1_ram_block1a11_PORT_A_data_out[0];


--M1_ram_block1a5 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|ram_block1a5
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
M1_ram_block1a5_PORT_A_data_in = P1L6;
M1_ram_block1a5_PORT_A_data_in_reg = DFFE(M1_ram_block1a5_PORT_A_data_in, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_PORT_A_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a5_PORT_A_address_reg = DFFE(M1_ram_block1a5_PORT_A_address, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_PORT_B_address = BUS(ram_addr[0], ram_addr[1], ram_addr[2], ram_addr[3], ram_addr[4], ram_addr[5], ram_addr[6], ram_addr[7], ram_addr[8], ram_addr[9], ram_addr[10], ram_addr[11]);
M1_ram_block1a5_PORT_B_address_reg = DFFE(M1_ram_block1a5_PORT_B_address, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_PORT_A_write_enable = GND;
M1_ram_block1a5_PORT_A_write_enable_reg = DFFE(M1_ram_block1a5_PORT_A_write_enable, M1_ram_block1a5_clock_0, , , M1_ram_block1a5_clock_enable_0);
M1_ram_block1a5_clock_0 = clk_5M;
M1_ram_block1a5_clock_enable_0 = !ram_addr[12];
M1_ram_block1a5_PORT_A_data_out = MEMORY(M1_ram_block1a5_PORT_A_data_in_reg, , M1_ram_block1a5_PORT_A_address_reg, M1_ram_block1a5_PORT_B_address_reg, M1_ram_block1a5_PORT_A_write_enable_reg, , , , M1_ram_block1a5_clock_0, , M1_ram_block1a5_clock_enable_0, , , );
M1_ram_block1a5 = M1_ram_block1a5_PORT_A_data_out[0];


--P1L6 is ram_8k_6:log_data_ram|lpm_ram_io:lpm_ram_io_component|altram:sram|altsyncram:ram_block|altsyncram_9l01:auto_generated|mux_fib:mux2|result_node[5]~77
P1L6 = M1_address_reg_a[0] & M1_ram_block1a11 # !M1_address_reg_a[0] & (M1_ram_block1a5);


--dv_temp_5 is dv_temp_5
dv_temp_5 = DFFEAS(dv_temp_4, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[12] is ram_addr[12]
ram_addr[12] = DFFEAS(A1L191, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[0] is ram_addr[0]
ram_addr[0] = DFFEAS(A1L192, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[1] is ram_addr[1]
ram_addr[1] = DFFEAS(A1L193, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[2] is ram_addr[2]
ram_addr[2] = DFFEAS(A1L194, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[3] is ram_addr[3]
ram_addr[3] = DFFEAS(A1L195, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[4] is ram_addr[4]
ram_addr[4] = DFFEAS(A1L196, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[5] is ram_addr[5]
ram_addr[5] = DFFEAS(A1L197, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[6] is ram_addr[6]
ram_addr[6] = DFFEAS(A1L198, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[7] is ram_addr[7]
ram_addr[7] = DFFEAS(A1L199, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[8] is ram_addr[8]
ram_addr[8] = DFFEAS(A1L200, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[9] is ram_addr[9]
ram_addr[9] = DFFEAS(A1L201, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[10] is ram_addr[10]
ram_addr[10] = DFFEAS(A1L202, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--ram_addr[11] is ram_addr[11]
ram_addr[11] = DFFEAS(A1L203, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--dv_temp_4 is dv_temp_4
dv_temp_4 = DFFEAS(dv_temp_3, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--R1_result[4] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[4]
--DSP Block Operation Mode: Simple Multiplier (18-bit)
R1_result[4] = DFFE(R1L5, clk_5M, , , );

--R1_result[5] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[5]
R1_result[5] = DFFE(R1L6, clk_5M, , , );

--R1_result[6] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[6]
R1_result[6] = DFFE(R1L7, clk_5M, , , );

--R1_result[7] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[7]
R1_result[7] = DFFE(R1L8, clk_5M, , , );

--R1_result[8] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[8]
R1_result[8] = DFFE(R1L9, clk_5M, , , );

--R1_result[9] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[9]
R1_result[9] = DFFE(R1L10, clk_5M, , , );

--R1_result[10] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[10]
R1_result[10] = DFFE(R1L11, clk_5M, , , );

--R1_result[11] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[11]
R1_result[11] = DFFE(R1L12, clk_5M, , , );

--R1_result[12] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[12]
R1_result[12] = DFFE(R1L13, clk_5M, , , );

--R1_result[13] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[13]
R1_result[13] = DFFE(R1L14, clk_5M, , , );

--R1_result[14] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[14]
R1_result[14] = DFFE(R1L15, clk_5M, , , );

--R1_result[15] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[15]
R1_result[15] = DFFE(R1L16, clk_5M, , , );

--R1_result[16] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[16]
R1_result[16] = DFFE(R1L17, clk_5M, , , );

--R1_result[17] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[17]
R1_result[17] = DFFE(R1L18, clk_5M, , , );

--R1_result[18] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[18]
R1_result[18] = DFFE(R1L19, clk_5M, , , );

--R1_result[19] is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|result[19]
R1_result[19] = DFFE(R1L20, clk_5M, , , );


--A1L191 is ram_addr~143
A1L191 = R1_result[16] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L192 is ram_addr~144
A1L192 = R1_result[4] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L193 is ram_addr~145
A1L193 = R1_result[5] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L194 is ram_addr~146
A1L194 = R1_result[6] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L195 is ram_addr~147
A1L195 = R1_result[7] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L196 is ram_addr~148
A1L196 = R1_result[8] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L197 is ram_addr~149
A1L197 = R1_result[9] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L198 is ram_addr~150
A1L198 = R1_result[10] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L199 is ram_addr~151
A1L199 = R1_result[11] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L200 is ram_addr~152
A1L200 = R1_result[12] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L201 is ram_addr~153
A1L201 = R1_result[13] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L202 is ram_addr~154
A1L202 = R1_result[14] # R1_result[17] # R1_result[18] # R1_result[19];


--A1L203 is ram_addr~155
A1L203 = R1_result[15] # R1_result[17] # R1_result[18] # R1_result[19];


--dv_temp_3 is dv_temp_3
dv_temp_3 = DFFEAS(dv_temp_2, clk_5M, !reset,  ,  ,  ,  ,  ,  );


--R1_mac_mult1 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1
--DSP Block Multiplier Base Width: 18-bits
R1_mac_mult1_a_data = DATA(mgc_mul_a[12], mgc_mul_a[11], mgc_mul_a[10], mgc_mul_a[9], mgc_mul_a[8], mgc_mul_a[7], mgc_mul_a[6], mgc_mul_a[5], mgc_mul_a[4], mgc_mul_a[3], mgc_mul_a[2], mgc_mul_a[1], mgc_mul_a[0]);
R1_mac_mult1_a_rep = ~GND ? SIGNED(R1_mac_mult1_a_data) : UNSIGNED(R1_mac_mult1_a_data);
R1_mac_mult1_b_data = DATA(mgc_mul_b[6], mgc_mul_b[5], mgc_mul_b[4], mgc_mul_b[3], mgc_mul_b[2], mgc_mul_b[1], mgc_mul_b[0]);
R1_mac_mult1_b_rep = ~GND ? SIGNED(R1_mac_mult1_b_data) : UNSIGNED(R1_mac_mult1_b_data);
R1_mac_mult1_result = R1_mac_mult1_a_rep * R1_mac_mult1_b_rep;
R1_mac_mult1 = R1_mac_mult1_result[0];

--R1L2 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT1
R1L2 = R1_mac_mult1_result[1];

--R1L3 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT2
R1L3 = R1_mac_mult1_result[2];

--R1L4 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT3
R1L4 = R1_mac_mult1_result[3];

--R1L5 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT4
R1L5 = R1_mac_mult1_result[4];

--R1L6 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT5
R1L6 = R1_mac_mult1_result[5];

--R1L7 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT6
R1L7 = R1_mac_mult1_result[6];

--R1L8 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT7
R1L8 = R1_mac_mult1_result[7];

--R1L9 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT8
R1L9 = R1_mac_mult1_result[8];

--R1L10 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT9
R1L10 = R1_mac_mult1_result[9];

--R1L11 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT10
R1L11 = R1_mac_mult1_result[10];

--R1L12 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT11
R1L12 = R1_mac_mult1_result[11];

--R1L13 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT12
R1L13 = R1_mac_mult1_result[12];

--R1L14 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT13
R1L14 = R1_mac_mult1_result[13];

--R1L15 is mul_13_7:mgc_mul|lpm_mult:lpm_mult_component|mult_vcs:auto_generated|mac_mult1~DATAOUT14