count60.vhd

自己做的vhdl课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
port(clk,clr:in std_logic;
en:in std_logic;
ql:out std_logic_vector(3 downto 0);
qh:out std_logic_vector(3 downto 0);
co:out std_logic);
end count60;
architecture behav of count60 is
signal qcl:std_logic_vector(3 downto 0);
signal qch:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clr='0')then
qcl<="0000";qch<="0000";
elsif(clk'event and clk='1')then
co<='0';
if(en='1'and qch<"0101"and qcl="1001")then
qcl<="0000";qch<="0000";co<='1';
else
if(en='1'and qcl<"1001")then
qcl<=qcl+'1';
else(en='1'and qcl="1001")then
qch<=qch+'1';qcl<="0000";
end if;
end if;
end if;
qh<=qch;
ql<=qcl;
end process;
end behav;