fdiv32.vhd

来自「自己做的vhdl课程设计」· VHDL 代码 · 共 36 行

-- 
--  File: fdiv32.vhd 
-- 	对1024HZ输入时钟分频得16HZ 
 
library IEEE; 
use IEEE.std_logic_1164.all;  
use IEEE.std_logic_unsigned.all; 
use IEEE.std_logic_arith.all; 
 
entity fdiv32 is 	 
	port ( 	     
		clkin: in STD_LOGIC; 
		clkout: out STD_LOGIC 
	); 
end fdiv32; 
 
architecture rtl of fdiv32 is 
signal cnt:integer range 0 to 32; 
signal clk:STD_LOGIC; 
begin  
	process(clkin) 
	begin 	 
		if rising_edge(clkin) then 
			if cnt=31 then 
				cnt<=0;	 
				clk<=not clk; 
			else cnt<=cnt+1; 
			end if; 
		end if; 
	end process;  
	 
	clkout<=clk; 
end rtl;