decode8.vhd

自己做的vhdl课程设计

library ieee;
use ieee.std_logic_1164.all;
entity decode8 is
port(data:in std_logic_vector(3 downto 0);
seg:out std_logic_vector(0 to 7));
end decode8;
architecture a of decode8 is
signal t:std_logic_vector(0 to 7);
begin 
process(data)
begin
case data is
when "0000"=>t<="11111100";
when "0001"=>t<="01100000";
when "0010"=>t<="11011010";
when "0011"=>t<="11110010";
when "0100"=>t<="01100110";
when "0101"=>t<="10110110";
when "0110"=>t<="00111110";
when "0111"=>t<="11100000";
when "1000"=>t<="11111110";
when "1001"=>t<="11100110";
when others=>t<="11111100";
end case;
seg<=t;
end process;
end a;