📄 travel.rpt
字号:
- 5 - A 09 DFFE 0 4 0 27 |FDIV8:6|clk (|FDIV8:6|:7)
- 2 - A 09 OR2 ! 0 3 0 1 |FDIV8:6|:25
- 1 - A 06 OR2 ! 0 3 0 2 |FDIV32:5|LPM_ADD_SUB:85|addcore:adder|:71
- 2 - A 06 OR2 ! 0 2 0 4 |FDIV32:5|LPM_ADD_SUB:85|addcore:adder|:75
- 3 - A 07 DFFE 1 2 0 2 |FDIV32:5|cnt5 (|FDIV32:5|:3)
- 1 - A 07 DFFE 1 1 0 3 |FDIV32:5|cnt4 (|FDIV32:5|:4)
- 6 - A 06 DFFE 1 2 0 1 |FDIV32:5|cnt3 (|FDIV32:5|:5)
- 3 - A 06 DFFE 1 3 0 1 |FDIV32:5|cnt2 (|FDIV32:5|:6)
- 4 - A 06 DFFE 1 2 0 2 |FDIV32:5|cnt1 (|FDIV32:5|:7)
- 5 - A 06 DFFE 1 0 0 3 |FDIV32:5|cnt0 (|FDIV32:5|:8)
- 4 - A 07 DFFE 1 3 0 5 |FDIV32:5|clk (|FDIV32:5|:9)
- 2 - A 07 OR2 ! 0 3 0 3 |FDIV32:5|:35
- 7 - C 23 OR2 s ! 0 4 0 4 |MUX8:7|~237~1
- 2 - A 18 OR2 0 4 0 1 |MUX8:7|:237
- 6 - C 23 AND2 0 3 0 4 |MUX8:7|:243
- 8 - C 23 OR2 ! 0 3 0 3 |MUX8:7|:253
- 8 - C 14 OR2 0 4 0 2 |MUX8:7|:256
- 5 - C 14 AND2 0 3 0 6 |MUX8:7|:263
- 1 - C 14 OR2 0 3 0 1 |MUX8:7|:266
- 4 - C 14 AND2 0 3 0 5 |MUX8:7|:273
- 3 - C 14 OR2 ! 0 4 0 3 |MUX8:7|:278
- 4 - C 22 OR2 ! 0 3 0 1 |MUX8:7|:289
- 2 - C 23 AND2 s 0 2 0 1 |MUX8:7|~297~1
- 4 - A 19 OR2 s 0 4 0 1 |MUX8:7|~297~2
- 5 - C 22 OR2 s 0 4 0 1 |MUX8:7|~297~3
- 5 - C 06 OR2 s 0 4 0 1 |MUX8:7|~297~4
- 1 - C 22 OR2 ! 0 4 0 4 |MUX8:7|:297
- 7 - A 19 OR2 s ! 0 2 0 1 |MUX8:7|~308~1
- 1 - A 19 OR2 ! 0 2 0 1 |MUX8:7|:308
- 1 - A 15 OR2 ! 0 4 0 1 |MUX8:7|:312
- 5 - A 15 OR2 ! 0 4 0 1 |MUX8:7|:314
- 1 - C 23 OR2 ! 0 4 0 1 |MUX8:7|:318
- 3 - C 04 OR2 ! 0 3 0 9 |MUX8:7|:321
- 2 - C 06 OR2 0 4 0 4 |MUX8:7|:324
- 6 - A 19 OR2 s ! 0 3 0 1 |MUX8:7|~333~1
- 2 - A 19 OR2 0 4 0 1 |MUX8:7|:338
- 3 - C 22 OR2 0 4 0 1 |MUX8:7|:341
- 3 - C 23 OR2 s ! 0 4 0 1 |MUX8:7|~342~1
- 2 - C 22 OR2 0 4 0 6 |MUX8:7|:345
- 4 - C 20 OR2 ! 0 4 0 4 |MUX8:7|:348
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\travel\travel.rpt
travel
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 30/ 96( 31%) 3/ 48( 6%) 22/ 48( 45%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 28/ 96( 29%) 20/ 48( 41%) 23/ 48( 47%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\travel\travel.rpt
travel
** CLOCK SIGNALS **
Type Fan-out Name
DFF 28 |FDIV8:6|clk
INPUT 10 clk
DFF 6 |FDIV32:5|clk
Device-Specific Information: e:\travel\travel.rpt
travel
** EQUATIONS **
clk : INPUT;
sa : INPUT;
sb : INPUT;
-- Node name is 'a0'
-- Equation name is 'a0', type is output
a0 = _LC2_C14;
-- Node name is 'a1'
-- Equation name is 'a1', type is output
a1 = _LC4_C23;
-- Node name is 'a2'
-- Equation name is 'a2', type is output
a2 = _LC5_C23;
-- Node name is 'ga'
-- Equation name is 'ga', type is output
ga = _LC4_A21;
-- Node name is 'gb'
-- Equation name is 'gb', type is output
gb = _LC6_A20;
-- Node name is 'ra'
-- Equation name is 'ra', type is output
ra = _LC6_A9;
-- Node name is 'rb'
-- Equation name is 'rb', type is output
rb = _LC8_A8;
-- Node name is 'seg0'
-- Equation name is 'seg0', type is output
seg0 = _LC2_C17;
-- Node name is 'seg1'
-- Equation name is 'seg1', type is output
seg1 = _LC3_C21;
-- Node name is 'seg2'
-- Equation name is 'seg2', type is output
seg2 = !_LC7_C17;
-- Node name is 'seg3'
-- Equation name is 'seg3', type is output
seg3 = _LC1_C17;
-- Node name is 'seg4'
-- Equation name is 'seg4', type is output
seg4 = _LC2_C20;
-- Node name is 'seg5'
-- Equation name is 'seg5', type is output
seg5 = _LC5_C17;
-- Node name is 'seg6'
-- Equation name is 'seg6', type is output
seg6 = _LC7_C21;
-- Node name is 'ya'
-- Equation name is 'ya', type is output
ya = _LC1_A8;
-- Node name is 'yb'
-- Equation name is 'yb', type is output
yb = _LC2_A8;
-- Node name is '|CONTROLLER:28|:57' = '|CONTROLLER:28|cnt'
-- Equation name is '_LC3_A11', type is buried
_LC3_A11 = DFFE( _EQ001, _LC5_A9, VCC, VCC, VCC);
_EQ001 = !_LC4_A8 & _LC4_A11
# _LC2_A11 & _LC4_A8;
-- Node name is '|CONTROLLER:28|:34' = '|CONTROLLER:28|counter0'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = DFFE( _EQ002, _LC5_A9, VCC, VCC, VCC);
_EQ002 = _LC2_A4 & !_LC6_A4;
-- Node name is '|CONTROLLER:28|:33' = '|CONTROLLER:28|counter1'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = DFFE( _EQ003, _LC5_A9, VCC, VCC, VCC);
_EQ003 = _LC1_A4 & _LC3_A11 & _LC4_A4 & !_LC6_A4
# _LC1_A4 & _LC3_A11 & !_LC4_A4 & _LC6_A4;
-- Node name is '|CONTROLLER:28|:32' = '|CONTROLLER:28|counter2'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = DFFE( _EQ004, _LC5_A9, VCC, VCC, VCC);
_EQ004 = _LC2_A4 & !_LC4_A4 & _LC8_A4
# _LC2_A4 & !_LC6_A4 & _LC8_A4
# _LC2_A4 & _LC4_A4 & _LC6_A4 & !_LC8_A4;
-- Node name is '|CONTROLLER:28|:31' = '|CONTROLLER:28|counter3'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE( _EQ005, _LC5_A9, VCC, VCC, VCC);
_EQ005 = _LC2_A4 & !_LC3_A4 & _LC5_A4
# _LC2_A4 & _LC3_A4 & !_LC5_A4;
-- Node name is '|CONTROLLER:28|:30' = '|CONTROLLER:28|counter4'
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = DFFE( _EQ006, _LC5_A9, VCC, VCC, VCC);
_EQ006 = _LC2_A4 & !_LC5_A4 & _LC7_A4
# _LC2_A4 & !_LC3_A4 & _LC7_A4
# _LC2_A4 & _LC3_A4 & _LC5_A4 & !_LC7_A4;
-- Node name is '|CONTROLLER:28|:39' = '|CONTROLLER:28|leda0'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = DFFE( _LC4_A8, _LC5_A9, VCC, VCC, VCC);
-- Node name is '|CONTROLLER:28|:38' = '|CONTROLLER:28|leda1'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = DFFE( _EQ007, _LC5_A9, VCC, VCC, VCC);
_EQ007 = !_LC3_A8 & _LC5_A11;
-- Node name is '|CONTROLLER:28|:37' = '|CONTROLLER:28|leda2'
-- Equation name is '_LC6_A9', type is buried
_LC6_A9 = DFFE( _EQ008, _LC5_A9, VCC, VCC, VCC);
_EQ008 = _LC3_A8 & !_LC4_A8
# !_LC4_A8 & !_LC5_A11;
-- Node name is '|CONTROLLER:28|:42' = '|CONTROLLER:28|ledb0'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = DFFE( _LC5_A8, _LC5_A9, VCC, VCC, VCC);
-- Node name is '|CONTROLLER:28|:41' = '|CONTROLLER:28|ledb1'
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = DFFE( _EQ009, _LC5_A9, VCC, VCC, VCC);
_EQ009 = _LC3_A8 & !_LC4_A8 & !_LC5_A8
# !_LC4_A8 & !_LC5_A8 & !_LC5_A11;
-- Node name is '|CONTROLLER:28|:40' = '|CONTROLLER:28|ledb2'
-- Equation name is '_LC8_A8', type is buried
_LC8_A8 = DFFE( _EQ010, _LC5_A9, VCC, VCC, VCC);
_EQ010 = !_LC3_A8 & _LC5_A11
# _LC4_A8;
-- Node name is '|CONTROLLER:28|LPM_ADD_SUB:586|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A12', type is buried
!_LC2_A12 = _LC2_A12~NOT;
_LC2_A12~NOT = LCELL( _EQ011);
_EQ011 = !_LC4_A4
# !_LC6_A4;
-- Node name is '|CONTROLLER:28|LPM_ADD_SUB:586|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ012);
_EQ012 = _LC4_A4 & _LC6_A4 & _LC8_A4;
-- Node name is '|CONTROLLER:28|LPM_ADD_SUB:696|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A12', type is buried
!_LC5_A12 = _LC5_A12~NOT;
_LC5_A12~NOT = LCELL( _EQ013);
_EQ013 = _LC4_A4 & _LC8_A4;
-- Node name is '|CONTROLLER:28|LPM_ADD_SUB:1055|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A20', type is buried
!_LC3_A20 = _LC3_A20~NOT;
_LC3_A20~NOT = LCELL( _EQ014);
_EQ014 = _LC4_A4 & _LC8_A4
# _LC6_A4 & _LC8_A4;
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