📄 travel.rpt
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Total I/O pins used: 19/60 ( 31%)
Total logic cells used: 209/576 ( 36%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.09/4 ( 77%)
Total fan-in: 647/2304 ( 28%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 209
Total flipflops required: 42
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 51/ 576 ( 8%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 8 0 6 4 8 8 0 8 8 0 8 8 5 0 0 7 7 7 3 8 0 0 103/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 6 8 0 8 8 8 8 8 0 7 0 0 8 0 0 8 0 0 8 8 5 8 0 106/0
Total: 0 0 6 16 0 14 12 16 16 8 8 15 0 8 16 5 0 8 7 7 15 11 13 8 0 209/0
Device-Specific Information: e:\travel\travel.rpt
travel
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
99 - - - 24 INPUT ^ 0 0 0 10 clk
98 - - - 24 INPUT ^ 0 0 0 4 sa
97 - - - 23 INPUT ^ 0 0 0 4 sb
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\travel\travel.rpt
travel
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
20 - - C -- OUTPUT 0 1 0 0 a0
21 - - C -- OUTPUT 0 1 0 0 a1
22 - - C -- OUTPUT 0 1 0 0 a2
96 - - - 22 OUTPUT 0 1 0 0 ga
94 - - - 19 OUTPUT 0 1 0 0 gb
86 - - - 09 OUTPUT 0 1 0 0 ra
85 - - - 08 OUTPUT 0 1 0 0 rb
6 - - A -- OUTPUT 0 1 0 0 seg0
7 - - A -- OUTPUT 0 1 0 0 seg1
9 - - A -- OUTPUT 0 1 0 0 seg2
13 - - B -- OUTPUT 0 1 0 0 seg3
14 - - B -- OUTPUT 0 1 0 0 seg4
15 - - B -- OUTPUT 0 1 0 0 seg5
16 - - B -- OUTPUT 0 1 0 0 seg6
71 - - A -- OUTPUT 0 1 0 0 ya
70 - - A -- OUTPUT 0 1 0 0 yb
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\travel\travel.rpt
travel
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 12 OR2 ! 0 2 0 1 |CONTROLLER:28|LPM_ADD_SUB:586|addcore:adder|:63
- 3 - A 04 AND2 0 3 0 2 |CONTROLLER:28|LPM_ADD_SUB:586|addcore:adder|:67
- 5 - A 12 AND2 ! 0 2 0 2 |CONTROLLER:28|LPM_ADD_SUB:696|addcore:adder|pcarry2
- 3 - A 20 OR2 ! 0 3 0 2 |CONTROLLER:28|LPM_ADD_SUB:1055|addcore:adder|pcarry2
- 4 - A 12 OR2 ! 0 2 0 1 |CONTROLLER:28|LPM_ADD_SUB:1055|addcore:adder|:63
- 7 - A 04 DFFE 0 4 0 6 |CONTROLLER:28|counter4 (|CONTROLLER:28|:30)
- 5 - A 04 DFFE 0 3 0 8 |CONTROLLER:28|counter3 (|CONTROLLER:28|:31)
- 8 - A 04 DFFE 0 4 0 9 |CONTROLLER:28|counter2 (|CONTROLLER:28|:32)
- 4 - A 04 DFFE 0 4 0 13 |CONTROLLER:28|counter1 (|CONTROLLER:28|:33)
- 6 - A 04 DFFE 0 2 0 12 |CONTROLLER:28|counter0 (|CONTROLLER:28|:34)
- 3 - A 08 DFFE 0 3 0 10 |CONTROLLER:28|state1 (|CONTROLLER:28|:35)
- 5 - A 11 DFFE 0 4 0 14 |CONTROLLER:28|state0 (|CONTROLLER:28|:36)
- 6 - A 09 DFFE 0 4 1 0 |CONTROLLER:28|leda2 (|CONTROLLER:28|:37)
- 1 - A 08 DFFE 0 3 1 0 |CONTROLLER:28|leda1 (|CONTROLLER:28|:38)
- 4 - A 21 DFFE 0 2 1 0 |CONTROLLER:28|leda0 (|CONTROLLER:28|:39)
- 8 - A 08 DFFE 0 4 1 0 |CONTROLLER:28|ledb2 (|CONTROLLER:28|:40)
- 2 - A 08 DFFE 0 5 1 0 |CONTROLLER:28|ledb1 (|CONTROLLER:28|:41)
- 6 - A 20 DFFE 0 2 1 0 |CONTROLLER:28|ledb0 (|CONTROLLER:28|:42)
- 7 - A 12 DFFE 0 5 0 23 |CONTROLLER:28|Num14 (|CONTROLLER:28|:43)
- 3 - A 12 DFFE 0 5 0 22 |CONTROLLER:28|Num13 (|CONTROLLER:28|:44)
- 8 - A 21 DFFE 0 4 0 10 |CONTROLLER:28|Num12 (|CONTROLLER:28|:45)
- 1 - A 21 DFFE 0 3 0 13 |CONTROLLER:28|Num11 (|CONTROLLER:28|:46)
- 7 - A 08 DFFE 0 4 0 11 |CONTROLLER:28|Num10 (|CONTROLLER:28|:47)
- 4 - A 20 DFFE 0 5 0 13 |CONTROLLER:28|Num24 (|CONTROLLER:28|:48)
- 8 - A 20 DFFE 0 4 0 12 |CONTROLLER:28|Num23 (|CONTROLLER:28|:49)
- 5 - A 20 DFFE 0 5 0 12 |CONTROLLER:28|Num22 (|CONTROLLER:28|:50)
- 1 - A 20 DFFE 0 4 0 8 |CONTROLLER:28|Num21 (|CONTROLLER:28|:51)
- 2 - A 20 DFFE 0 3 0 8 |CONTROLLER:28|Num20 (|CONTROLLER:28|:52)
- 3 - A 19 DFFE 0 4 0 3 |CONTROLLER:28|Num32 (|CONTROLLER:28|:53)
- 5 - A 19 DFFE 0 3 0 3 |CONTROLLER:28|Num31 (|CONTROLLER:28|:54)
- 6 - A 08 DFFE 0 3 0 1 |CONTROLLER:28|Num30 (|CONTROLLER:28|:55)
- 3 - A 11 DFFE 0 4 0 2 |CONTROLLER:28|cnt (|CONTROLLER:28|:57)
- 6 - A 12 OR2 s 0 4 0 2 |CONTROLLER:28|~735~1
- 8 - A 11 OR2 2 2 0 1 |CONTROLLER:28|:813
- 2 - A 11 OR2 2 2 0 1 |CONTROLLER:28|:831
- 8 - A 12 OR2 ! 0 4 0 3 |CONTROLLER:28|:910
- 1 - A 12 OR2 ! 0 4 0 2 |CONTROLLER:28|:1092
- 6 - A 11 OR2 2 1 0 1 |CONTROLLER:28|:1225
- 1 - A 11 OR2 2 1 0 1 |CONTROLLER:28|:1288
- 5 - A 08 OR2 ! 0 2 0 7 |CONTROLLER:28|:1487
- 4 - A 08 AND2 0 2 0 10 |CONTROLLER:28|:1503
- 2 - A 04 AND2 s 0 2 0 4 |CONTROLLER:28|~1530~1
- 1 - A 04 OR2 s 0 2 0 2 |CONTROLLER:28|~1554~1
- 7 - A 11 OR2 0 4 0 1 |CONTROLLER:28|:1803
- 4 - A 11 OR2 0 4 0 2 |CONTROLLER:28|:1827
- 3 - C 06 OR2 0 2 0 6 |CONTROLLER:28|:2058
- 1 - C 08 AND2 0 2 0 6 |CONTROLLER:28|:2060
- 5 - C 08 OR2 ! 0 2 0 5 |CONTROLLER:28|:2093
- 6 - C 08 OR2 ! 0 4 0 7 |CONTROLLER:28|:2136
- 3 - C 03 AND2 s 0 2 0 4 |CONTROLLER:28|~2200~1
- 8 - C 09 AND2 0 2 0 1 |CONTROLLER:28|:2200
- 7 - C 08 AND2 s 0 2 0 7 |CONTROLLER:28|~2211~1
- 5 - C 09 OR2 ! 0 2 0 1 |CONTROLLER:28|:2211
- 3 - C 09 AND2 s ! 0 2 0 3 |CONTROLLER:28|~2222~1
- 6 - C 09 AND2 0 2 0 1 |CONTROLLER:28|:2222
- 4 - C 08 OR2 s 0 2 0 3 |CONTROLLER:28|~2233~1
- 2 - C 09 OR2 ! 0 2 0 1 |CONTROLLER:28|:2233
- 5 - C 03 OR2 s ! 0 3 0 3 |CONTROLLER:28|~2255~1
- 8 - C 08 AND2 0 4 0 2 |CONTROLLER:28|:2266
- 1 - C 12 OR2 ! 0 4 0 3 |CONTROLLER:28|:2277
- 4 - C 03 AND2 0 3 0 3 |CONTROLLER:28|:2431
- 5 - C 04 OR2 s 0 3 0 2 |CONTROLLER:28|~2455~1
- 2 - C 04 OR2 s 0 3 0 2 |CONTROLLER:28|~2485~1
- 7 - C 04 OR2 ! 0 4 0 1 |CONTROLLER:28|:2485
- 2 - C 03 OR2 0 4 0 1 |CONTROLLER:28|:2503
- 4 - C 09 OR2 0 4 0 1 |CONTROLLER:28|:2509
- 7 - C 09 OR2 0 4 0 1 |CONTROLLER:28|:2523
- 1 - C 10 AND2 s 0 2 0 3 |CONTROLLER:28|~2595~1
- 4 - C 06 OR2 s 0 2 0 4 |CONTROLLER:28|~2617~1
- 6 - C 10 AND2 s ! 0 2 0 2 |CONTROLLER:28|~2628~1
- 1 - C 03 OR2 ! 0 3 0 2 |CONTROLLER:28|:2650
- 3 - C 12 OR2 s 0 2 0 4 |CONTROLLER:28|~2661~1
- 6 - C 03 OR2 s 0 3 0 1 |CONTROLLER:28|~2672~1
- 4 - C 07 OR2 s 0 3 0 2 |CONTROLLER:28|~2850~1
- 6 - C 06 OR2 ! 0 3 0 1 |CONTROLLER:28|:2850
- 7 - C 06 OR2 ! 0 3 0 1 |CONTROLLER:28|:2868
- 8 - C 06 OR2 s 0 2 0 1 |CONTROLLER:28|~2880~1
- 3 - C 08 OR2 0 4 0 1 |CONTROLLER:28|:2898
- 2 - C 07 OR2 0 4 0 1 |CONTROLLER:28|:2904
- 3 - C 07 OR2 0 4 0 1 |CONTROLLER:28|:2910
- 5 - C 07 OR2 0 4 0 1 |CONTROLLER:28|:2916
- 8 - C 07 AND2 0 3 0 1 |CONTROLLER:28|:2990
- 6 - C 07 OR2 ! 0 4 0 1 |CONTROLLER:28|:3001
- 2 - C 08 OR2 s 0 3 0 4 |CONTROLLER:28|~3012~1
- 6 - C 12 AND2 s 0 2 0 1 |CONTROLLER:28|~3045~1
- 1 - C 04 AND2 0 3 0 3 |CONTROLLER:28|:3221
- 7 - C 10 OR2 s 0 3 0 2 |CONTROLLER:28|~3245~1
- 8 - C 10 OR2 ! 0 3 0 1 |CONTROLLER:28|:3263
- 4 - C 12 OR2 s 0 4 0 2 |CONTROLLER:28|~3275~1
- 4 - C 10 OR2 ! 0 3 0 1 |CONTROLLER:28|:3275
- 5 - C 12 OR2 0 4 0 1 |CONTROLLER:28|:3293
- 7 - C 12 OR2 0 4 0 1 |CONTROLLER:28|:3299
- 2 - C 12 OR2 0 3 0 1 |CONTROLLER:28|:3307
- 7 - C 07 OR2 0 4 0 1 |CONTROLLER:28|:3313
- 6 - C 14 OR2 0 3 0 1 |CONTROLLER:28|:3370
- 3 - C 10 OR2 0 4 0 1 |CONTROLLER:28|:3371
- 7 - C 14 OR2 0 3 0 2 |CONTROLLER:28|:3373
- 5 - C 10 OR2 ! 0 4 0 1 |CONTROLLER:28|:3381
- 4 - C 04 OR2 ! 0 4 0 1 |CONTROLLER:28|:3383
- 6 - C 04 OR2 ! 0 4 0 1 |CONTROLLER:28|:3388
- 2 - C 10 OR2 s 0 4 0 2 |CONTROLLER:28|~3389~1
- 1 - C 06 OR2 ! 0 4 0 1 |CONTROLLER:28|:3389
- 8 - C 04 OR2 ! 0 4 0 1 |CONTROLLER:28|:3391
- 1 - C 07 OR2 0 4 0 1 |CONTROLLER:28|:3397
- 1 - C 09 OR2 0 4 0 1 |CONTROLLER:28|:3400
- 4 - A 18 AND2 0 3 0 3 |CONTROLLER:28|:3408
- 1 - A 14 AND2 0 2 0 1 |CONTROLLER:28|:3449
- 3 - A 22 AND2 s 0 3 0 3 |CONTROLLER:28|~3469~1
- 2 - A 22 OR2 0 4 0 7 |CONTROLLER:28|:3469
- 7 - A 13 OR2 s ! 0 2 0 2 |CONTROLLER:28|~3604~1
- 6 - A 22 AND2 0 3 0 1 |CONTROLLER:28|:3615
- 4 - A 22 AND2 s ! 0 3 0 2 |CONTROLLER:28|~3626~1
- 5 - A 22 AND2 0 2 0 3 |CONTROLLER:28|:3780
- 1 - A 13 OR2 s 0 4 0 2 |CONTROLLER:28|~3804~1
- 2 - A 15 OR2 ! 0 3 0 1 |CONTROLLER:28|:3833
- 7 - A 22 OR2 s 0 2 0 2 |CONTROLLER:28|~3834~1
- 2 - A 13 OR2 0 4 0 1 |CONTROLLER:28|:3852
- 7 - A 14 OR2 0 4 0 1 |CONTROLLER:28|:3858
- 8 - A 14 OR2 0 3 0 1 |CONTROLLER:28|:3870
- 1 - A 22 AND2 s 0 3 0 2 |CONTROLLER:28|~3955~1
- 4 - A 13 AND2 s ! 0 2 0 2 |CONTROLLER:28|~3966~1
- 8 - A 22 OR2 s ! 0 3 0 4 |CONTROLLER:28|~3999~1
- 8 - A 13 OR2 s 0 3 0 5 |CONTROLLER:28|~4010~1
- 6 - A 13 OR2 s 0 3 0 4 |CONTROLLER:28|~4021~1
- 3 - A 18 AND2 0 2 0 3 |CONTROLLER:28|:4175
- 5 - A 18 OR2 s 0 2 0 1 |CONTROLLER:28|~4199~1
- 5 - A 13 OR2 ! 0 4 0 1 |CONTROLLER:28|:4217
- 7 - A 18 OR2 ! 0 3 0 1 |CONTROLLER:28|:4228
- 3 - A 13 OR2 s 0 4 0 2 |CONTROLLER:28|~4229~1
- 3 - A 14 AND2 0 3 0 1 |CONTROLLER:28|:4247
- 4 - A 14 OR2 0 4 0 1 |CONTROLLER:28|:4253
- 5 - A 14 OR2 0 4 0 1 |CONTROLLER:28|:4259
- 6 - A 14 OR2 0 4 0 1 |CONTROLLER:28|:4265
- 4 - A 15 OR2 ! 0 4 0 1 |CONTROLLER:28|:4334
- 6 - A 18 OR2 ! 0 4 0 1 |CONTROLLER:28|:4335
- 3 - A 15 OR2 ! 0 4 0 1 |CONTROLLER:28|:4343
- 1 - A 18 OR2 ! 0 4 0 1 |CONTROLLER:28|:4344
- 2 - A 14 OR2 0 3 0 1 |CONTROLLER:28|:4351
- 5 - C 23 DFFE 1 2 1 9 |COUNT8:2|qc12 (|COUNT8:2|:5)
- 4 - C 23 DFFE 1 1 1 10 |COUNT8:2|qc11 (|COUNT8:2|:6)
- 2 - C 14 DFFE 1 0 1 11 |COUNT8:2|qc10 (|COUNT8:2|:7)
- 7 - C 20 OR2 s ! 0 3 0 2 |DECODE8:30|~274~1
- 6 - C 20 OR2 s 0 3 0 5 |DECODE8:30|~298~1
- 8 - C 21 OR2 ! 0 3 0 2 |DECODE8:30|:298
- 1 - C 21 OR2 s ! 0 2 0 3 |DECODE8:30|~310~1
- 5 - C 21 AND2 0 2 0 1 |DECODE8:30|:334
- 7 - C 17 AND2 0 3 1 0 |DECODE8:30|:358
- 4 - C 17 AND2 s 0 2 0 5 |DECODE8:30|~361~1
- 4 - C 21 OR2 0 2 0 1 |DECODE8:30|:361
- 6 - C 17 OR2 ! 0 3 0 4 |DECODE8:30|:370
- 3 - C 20 OR2 s ! 0 3 0 5 |DECODE8:30|~382~1
- 3 - C 17 AND2 0 3 0 4 |DECODE8:30|:382
- 2 - C 17 OR2 0 3 1 0 |DECODE8:30|:385
- 2 - C 21 OR2 0 3 0 2 |DECODE8:30|:408
- 8 - C 17 OR2 s 0 2 0 2 |DECODE8:30|~418~1
- 3 - C 21 OR2 0 4 1 0 |DECODE8:30|:418
- 1 - C 20 OR2 0 4 0 1 |DECODE8:30|:477
- 1 - C 17 OR2 0 4 1 0 |DECODE8:30|:484
- 8 - C 20 OR2 s 0 4 0 1 |DECODE8:30|~513~1
- 2 - C 20 OR2 0 3 1 0 |DECODE8:30|:517
- 5 - C 17 OR2 0 4 1 0 |DECODE8:30|:550
- 5 - C 20 AND2 s 0 3 0 1 |DECODE8:30|~567~1
- 6 - C 21 OR2 s 0 4 0 1 |DECODE8:30|~577~1
- 7 - C 21 OR2 0 4 1 0 |DECODE8:30|:585
- 1 - A 09 OR2 ! 0 2 0 4 |FDIV8:6|LPM_ADD_SUB:61|addcore:adder|:59
- 8 - A 09 DFFE 0 3 0 2 |FDIV8:6|cnt3 (|FDIV8:6|:3)
- 7 - A 09 DFFE 0 2 0 3 |FDIV8:6|cnt2 (|FDIV8:6|:4)
- 3 - A 09 DFFE 0 3 0 1 |FDIV8:6|cnt1 (|FDIV8:6|:5)
- 4 - A 09 DFFE 0 1 0 2 |FDIV8:6|cnt0 (|FDIV8:6|:6)
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