seg7decd.vhd

自己做的vhdl课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.alL;
use ieee.std_logic_unsigned.all;
entity seg7decd is
port(
clk:in std_logic;
data:in std_logic_vector(3 downto 0);
segout:out std_logic_vector(7 downto 0);
selout:out std_logic_vector(7 downto 0));
end seg7decd;
architecture a of seg7decd is
signal s:std_logic_vector(2 downto 0);
signal num:std_logic_vector(3 downto 0);
signal seg:std_logic_vector(6 downto 0);
signal sel:std_logic_vector(7 downto 0);
begin
connection:block
begin
selout<=sel;
segout(6 downto 0)<=seg;
segout(7)<='0';
num<=data;
end block connection;
counter:block
signal q:std_logic_vector(24 downto 0);
begin
process(clk)
begin
if clk'event and clk='1'then
q<=q+1;
end if;
end process;
s<=q(3 downto 0);
sel<="11111110"when s=0 else
"11111101"when s=1 else
"11111011"when s=2 else
"11110111"when s=3 else
"11101111"when s=4 else
"11011111"when s=5 else
"10111111"when s=6 else
"01111111"when s=7 else
"11111111";
end block counter;
dec:block
begin
seg<="0111111"when num=0 else
"0000110"when num= 1 else
"1011011"when num=2 else
"1001111"when num= 3 else
"1100110"when num=4 else
"1101101"when num=5 else
"1111101"when num=6 else
"0000111"when num=7 else
"1111111"when num=8 else
"1101111"when num=9 else
"1110111"when num=10 else
"1111100"when num=11 else
"0111001"when num=12 else
"1011110"when num=13 else
"1111001"when num=14 else
"1111001"when num=15 else
"0000000";
end block dec;
end a;