mux8.vhd

自己做的vhdl课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux8 is
port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic_vector(3 downto 0);
a:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0));
end mux8;
architecture a of mux8 is
begin
process(a)
begin
case a is
when"000"=>y<=d0;
when"001"=>y<=d1;
when"010"=>y<=d2;
when"011"=>y<=d3;
when"100"=>y<=d4;
when"101"=>y<=d5;
when"110"=>y<=d6;
when"111"=>y<=d7;
when others=>y<="XXXX";
end case;
end process;
end a;