seg7decd.rpt

自己做的vhdl课程设计

         # !q2;

-- Node name is ':579' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = LCELL( _EQ011);
  _EQ011 = !data0 & !data1 & !data2 & !data3;

-- Node name is ':584' 
-- Equation name is '_LC1_B5', type is buried 
!_LC1_B5 = _LC1_B5~NOT;
_LC1_B5~NOT = LCELL( _EQ012);
  _EQ012 =  data1
         # !data0
         #  data3
         #  data2;

-- Node name is ':589' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = LCELL( _EQ013);
  _EQ013 = !data0 &  data1 & !data2 & !data3;

-- Node name is ':599' 
-- Equation name is '_LC1_B3', type is buried 
!_LC1_B3 = _LC1_B3~NOT;
_LC1_B3~NOT = LCELL( _EQ014);
  _EQ014 =  data1
         #  data0
         #  data3
         # !data2;

-- Node name is ':614' 
-- Equation name is '_LC1_B7', type is buried 
_LC1_B7  = LCELL( _EQ015);
  _EQ015 =  data0 &  data1 &  data2 & !data3;

-- Node name is ':629' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ016);
  _EQ016 = !data0 &  data1 & !data2 &  data3;

-- Node name is ':760' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = LCELL( _EQ017);
  _EQ017 =  data1 &  data3
         #  data1 & !data2
         # !data0 &  data1
         # !data2 &  data3
         #  data0 &  data3
         # !data0 &  data2 & !data3
         #  data0 & !data1 &  data2;

-- Node name is '~785~1' 
-- Equation name is '~785~1', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EQ018);
  _EQ018 = !data1 & !data2 &  data3;

-- Node name is ':809' 
-- Equation name is '_LC3_B10', type is buried 
_LC3_B10 = LCELL( _EQ019);
  _EQ019 = !data2 &  data3
         # !data0 &  data3
         #  data1 &  data3
         # !data0 & !data1
         # !data1 &  data2 & !data3
         # !data0 &  data2;

-- Node name is ':854' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = LCELL( _EQ020);
  _EQ020 =  _LC3_B8
         # !_LC1_B3 &  _LC1_B8;

-- Node name is '~856~1' 
-- Equation name is '~856~1', location is LC1_B8, type is buried.
-- synthesized logic cell 
_LC1_B8  = LCELL( _EQ021);
  _EQ021 = !data0 & !data2 &  data3
         #  data1 & !data2 &  data3
         #  data0 &  data2 &  data3
         # !data0 &  data1 &  data2
         #  data0 &  data1 &  data3
         # !data0 & !data1 &  data3;

-- Node name is ':860' 
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = LCELL( _EQ022);
  _EQ022 = !_LC1_B5 &  _LC2_B8
         #  _LC1_B6;

-- Node name is ':878' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ023);
  _EQ023 =  data0 &  data1 &  data3
         #  data2 &  data3;

-- Node name is ':887' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ024);
  _EQ024 =  _LC2_B4 & !_LC3_B4
         #  _LC5_B4;

-- Node name is ':904' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ025);
  _EQ025 = !_LC1_B3 &  _LC1_B4 & !_LC1_B7
         # !_LC1_B3 &  _LC4_B2;

-- Node name is ':911' 
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ026);
  _EQ026 =  _LC1_B2 & !_LC1_B5
         # !_LC1_B5 &  _LC6_B2
         #  _LC1_B6;

-- Node name is ':962' 
-- Equation name is '_LC1_B11', type is buried 
_LC1_B11 = LCELL( _EQ027);
  _EQ027 = !data1 & !data3
         #  data2 & !data3
         #  data0 & !data1
         # !data2 &  data3
         # !data1 & !data2
         #  data0 & !data2
         #  data0 & !data3;

-- Node name is '~992~1' 
-- Equation name is '~992~1', location is LC4_B4, type is buried.
-- synthesized logic cell 
_LC4_B4  = LCELL( _EQ028);
  _EQ028 =  _LC1_B7
         #  _LC3_B4
         #  _LC5_B4;

-- Node name is ':1013' 
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ029);
  _EQ029 = !data0 & !data1 & !data3
         # !data2 & !data3
         #  data0 & !data1 &  data3
         # !data0 & !data2
         # !data1 & !data2
         #  data0 &  data1 & !data3;

-- Node name is ':1036' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ030);
  _EQ030 = !data0 &  data2 &  data3
         #  data1 &  data2 &  data3;

-- Node name is '~1049~1' 
-- Equation name is '~1049~1', location is LC4_B2, type is buried.
-- synthesized logic cell 
_LC4_B2  = LCELL( _EQ031);
  _EQ031 =  data0 & !data1 &  data2 & !data3
         # !data0 &  data1 &  data2 & !data3;

-- Node name is ':1057' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = LCELL( _EQ032);
  _EQ032 = !_LC1_B3 &  _LC4_B2
         # !_LC1_B3 &  _LC4_B4
         # !_LC1_B3 &  _LC3_B2;

-- Node name is '~1058~1' 
-- Equation name is '~1058~1', location is LC6_B2, type is buried.
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ033);
  _EQ033 =  data1 & !data2 & !data3;

-- Node name is ':1064' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ034);
  _EQ034 =  _LC1_B6
         # !_LC1_B5 &  _LC6_B2
         # !_LC1_B5 &  _LC5_B2;



Project Information                                       e:\test\seg7decd.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 9,721K